Michal Simek
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2c97ec5842
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clk: zynq: Use clk_readl/clk_writel helper function
Do not use readl/writel directly because the whole
clk subsystem is using clk_readl/clk_writel functions.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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2014-02-25 14:08:48 -08:00 |
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Soren Brinkmann
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353dc6c47d
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clk/zynq/pll: Use #defines for fbdiv min/max values
Use more descriptive #defines for the minimum and maximum PLL
feedback divider.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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2013-08-20 07:54:41 +02:00 |
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Soren Brinkmann
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14924ba288
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clk/zynq/pll: Fix documentation for PLL register function
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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2013-08-20 07:54:40 +02:00 |
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Soren Brinkmann
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3682af46d5
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clk: zynq: Factor out PLL driver
Refactor the PLL driver so it works with the clock controller driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
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2013-05-21 16:21:35 +02:00 |
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