Ralf Baechle
f7777dcc75
MIPS: Panic messages should not end in \n.
...
Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2013-10-29 21:24:19 +01:00
John Crispin
d0c550dc36
MIPS: lantiq: add GPHY clock gate bits
...
Explicitly enable the clock gate of the internal GPHYs found on xrx200.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4816/
2013-02-17 00:15:17 +01:00
John Crispin
740c606e8e
MIPS: lantiq: adds static clock for PP32
...
The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-17 00:15:17 +01:00
John Crispin
3d18c17e4f
MIPS: lantiq: trivial typo fix
...
"nodes" is written with a single "s"
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4814/
2013-02-17 00:15:16 +01:00
John Crispin
f2bbe41c50
MIPS: lantiq: adds xrx200 ethernet clock definition
...
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4521
2012-11-11 18:47:31 +01:00
Ralf Baechle
382fc33b4a
Merge branch 'master' of git://dev.phrozen.org/mips-next into mips-for-linux-next
2012-10-05 15:56:28 +02:00
John Crispin
f40e1f9d85
MIPS: lantiq: enable pci clk conditional for xrx200 SoC
...
The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4235/
2012-08-23 00:08:18 +02:00
John Crispin
98dbc5764d
MIPS: lantiq: explicitly enable clkout generation
...
Previously we relied on the bootloader to have enabled this bit. However some
bootloaders seem to not enable this for us.
Signed-off-by: John Crispin <blogic@openwrt.org >
Patchwork: http://patchwork.linux-mips.org/patch/4120/
2012-08-22 23:46:37 +02:00
John Crispin
e29b72f5e1
MIPS: Lantiq: Fix interface clock and PCI control register offset
...
The XRX200 based SoC have a different register offset for the interface
clock and PCI control registers. This patch detects the SoC and sets the
register offset at runtime. This make PCI work on the VR9 SoC.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4113/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-08-01 17:57:04 +02:00
John Crispin
009d6914f1
MIPS: lantiq: remove orphaned code
...
Now that all drivers are converted to OF we are able to remove some remaining
pieces of orphaned code.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-05-26 19:52:57 +01:00
John Crispin
287e3f3f4e
MIPS: lantiq: implement support for clkdev api
...
This patch unifies all clock generation and gating code into one file.
All drivers will now be able to request their clocks via their device.
This patch also adds support for the clockout feature, which allows
clock generation on external pins.
Support for COMMON_CLK will be provided in the next series.
Signed-off-by: John Crispin <blogic@openwrt.org >
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3804/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org >
2012-05-21 14:31:51 +01:00
