Merge tag 'xtensa-next-20160320' of git://github.com/czankel/xtensa-linux
Pull Xtensa updates from Chris Zankel:
"Xtensa improvements for 4.6:
- control whether perf IRQ is treated as NMI from Kconfig
- implement ioremap for regions outside KIO segment
- fix ISS serial port behaviour when EOF is reached
- fix preemption in {clear,copy}_user_highpage
- fix endianness issues for XTFPGA devices, big-endian cores are now
fully functional
- clean up debug infrastructure and add support for hardware
breakpoints and watchpoints
- add processor configurations for Three Core HiFi-2 MX and HiFi3
cpus"
* tag 'xtensa-next-20160320' of git://github.com/czankel/xtensa-linux:
xtensa: add test_kc705_hifi variant
xtensa: add Three Core HiFi-2 MX Variant.
xtensa: support hardware breakpoints/watchpoints
xtensa: use context structure for debug exceptions
xtensa: remove remaining non-functional KGDB bits
xtensa: clear all DBREAKC registers on start
xtensa: xtfpga: fix earlycon endianness
xtensa: xtfpga: fix i2c controller register width and endianness
xtensa: xtfpga: fix ethernet controller endianness
xtensa: xtfpga: fix serial port register width and endianness
xtensa: define CONFIG_CPU_{BIG,LITTLE}_ENDIAN
xtensa: fix preemption in {clear,copy}_user_highpage
xtensa: ISS: don't hang if stdin EOF is reached
xtensa: support ioremap for memory outside KIO region
xtensa: use XTENSA_INT_LEVEL macro in asm/timex.h
xtensa: make fake NMI configurable
This commit is contained in:
Linus Torvalds
@@ -8,12 +8,12 @@ obj-y := align.o coprocessor.o entry.o irq.o pci-dma.o platform.o process.o \
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ptrace.o setup.o signal.o stacktrace.o syscall.o time.o traps.o \
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vectors.o
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obj-$(CONFIG_KGDB) += xtensa-stub.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
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obj-$(CONFIG_FUNCTION_TRACER) += mcount.o
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obj-$(CONFIG_SMP) += smp.o mxhead.o
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obj-$(CONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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AFLAGS_head.o += -mtext-section-literals
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AFLAGS_mxhead.o += -mtext-section-literals
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@@ -23,6 +23,7 @@
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#include <linux/kbuild.h>
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#include <asm/ptrace.h>
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#include <asm/traps.h>
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#include <asm/uaccess.h>
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int main(void)
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@@ -117,5 +118,16 @@ int main(void)
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DEFINE(_CLONE_UNTRACED, CLONE_UNTRACED);
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DEFINE(PG_ARCH_1, PG_arch_1);
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/* struct debug_table */
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DEFINE(DT_DEBUG_EXCEPTION,
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offsetof(struct debug_table, debug_exception));
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DEFINE(DT_DEBUG_SAVE, offsetof(struct debug_table, debug_save));
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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DEFINE(DT_DBREAKC_SAVE, offsetof(struct debug_table, dbreakc_save));
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DEFINE(DT_ICOUNT_SAVE, offsetof(struct debug_table, icount_save));
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DEFINE(DT_ICOUNT_LEVEL_SAVE,
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offsetof(struct debug_table, icount_level_save));
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#endif
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return 0;
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}
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@@ -543,6 +543,12 @@ common_exception_return:
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#endif
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5:
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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_bbci.l a4, TIF_DB_DISABLED, 7f
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movi a4, restore_dbreak
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callx4 a4
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7:
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#endif
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#ifdef CONFIG_DEBUG_TLB_SANITY
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l32i a4, a1, PT_DEPC
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bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
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@@ -789,39 +795,99 @@ ENTRY(debug_exception)
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movi a2, 1 << PS_EXCM_BIT
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or a2, a0, a2
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movi a0, debug_exception # restore a3, debug jump vector
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wsr a2, ps
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xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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/* Switch to kernel/user stack, restore jump vector, and save a0 */
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bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
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addi a2, a1, -16-PT_SIZE # assume kernel stack
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3:
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l32i a0, a3, DT_DEBUG_SAVE
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s32i a1, a2, PT_AREG1
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s32i a0, a2, PT_AREG0
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movi a0, 0
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s32i a1, a2, PT_AREG1
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s32i a0, a2, PT_DEPC # mark it as a regular exception
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xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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xsr a0, depc
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s32i a3, a2, PT_AREG3
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s32i a0, a2, PT_AREG2
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mov a1, a2
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/* Debug exception is handled as an exception, so interrupts will
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* likely be enabled in the common exception handler. Disable
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* preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM
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* meaning.
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*/
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#if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT)
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GET_THREAD_INFO(a2, a1)
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l32i a3, a2, TI_PRE_COUNT
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addi a3, a3, 1
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s32i a3, a2, TI_PRE_COUNT
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#endif
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rsr a2, ps
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bbsi.l a2, PS_UM_BIT, _user_exception
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j _kernel_exception
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2: rsr a2, excsave1
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l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
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s32i a0, a2, PT_AREG0
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movi a0, 0
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s32i a1, a2, PT_AREG1
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s32i a0, a2, PT_DEPC
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xsr a0, depc
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s32i a3, a2, PT_AREG3
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s32i a0, a2, PT_AREG2
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mov a1, a2
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j _user_exception
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j 3b
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/* Debug exception while in exception mode. */
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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/* Debug exception while in exception mode. This may happen when
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* window overflow/underflow handler or fast exception handler hits
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* data breakpoint, in which case save and disable all data
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* breakpoints, single-step faulting instruction and restore data
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* breakpoints.
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*/
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1:
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bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode
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rsr a0, debugcause
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bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak
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.set _index, 0
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.rept XCHAL_NUM_DBREAK
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l32i a0, a3, DT_DBREAKC_SAVE + _index * 4
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wsr a0, SREG_DBREAKC + _index
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.set _index, _index + 1
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.endr
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l32i a0, a3, DT_ICOUNT_LEVEL_SAVE
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wsr a0, icountlevel
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l32i a0, a3, DT_ICOUNT_SAVE
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xsr a0, icount
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l32i a0, a3, DT_DEBUG_SAVE
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xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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rfi XCHAL_DEBUGLEVEL
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.Ldebug_save_dbreak:
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.set _index, 0
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.rept XCHAL_NUM_DBREAK
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movi a0, 0
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xsr a0, SREG_DBREAKC + _index
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s32i a0, a3, DT_DBREAKC_SAVE + _index * 4
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.set _index, _index + 1
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.endr
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movi a0, XCHAL_EXCM_LEVEL + 1
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xsr a0, icountlevel
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s32i a0, a3, DT_ICOUNT_LEVEL_SAVE
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movi a0, 0xfffffffe
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xsr a0, icount
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s32i a0, a3, DT_ICOUNT_SAVE
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l32i a0, a3, DT_DEBUG_SAVE
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xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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rfi XCHAL_DEBUGLEVEL
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#else
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/* Debug exception while in exception mode. Should not happen. */
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1: j 1b // FIXME!!
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#endif
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ENDPROC(debug_exception)
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@@ -128,7 +128,7 @@ ENTRY(_startup)
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wsr a0, icountlevel
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.set _index, 0
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.rept XCHAL_NUM_DBREAK - 1
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.rept XCHAL_NUM_DBREAK
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wsr a0, SREG_DBREAKC + _index
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.set _index, _index + 1
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.endr
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@@ -197,11 +197,6 @@ ENTRY(_startup)
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wsr a2, ps # (enable reg-windows; progmode stack)
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rsync
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/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
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movi a2, debug_exception
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wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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#ifdef CONFIG_SMP
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/*
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* Notice that we assume with SMP that cores have PRID
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317
arch/xtensa/kernel/hw_breakpoint.c
Normal file
317
arch/xtensa/kernel/hw_breakpoint.c
Normal file
@@ -0,0 +1,317 @@
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/*
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* Xtensa hardware breakpoints/watchpoints handling functions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*/
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#include <linux/hw_breakpoint.h>
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#include <linux/log2.h>
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#include <linux/percpu.h>
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#include <linux/perf_event.h>
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#include <variant/core.h>
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/* Breakpoint currently in use for each IBREAKA. */
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static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
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/* Watchpoint currently in use for each DBREAKA. */
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static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
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int hw_breakpoint_slots(int type)
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{
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switch (type) {
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case TYPE_INST:
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return XCHAL_NUM_IBREAK;
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case TYPE_DATA:
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return XCHAL_NUM_DBREAK;
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default:
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pr_warn("unknown slot type: %d\n", type);
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return 0;
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}
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}
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int arch_check_bp_in_kernelspace(struct perf_event *bp)
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{
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unsigned int len;
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unsigned long va;
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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va = info->address;
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len = bp->attr.bp_len;
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
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}
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/*
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* Construct an arch_hw_breakpoint from a perf_event.
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*/
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static int arch_build_bp_info(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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/* Type */
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switch (bp->attr.bp_type) {
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case HW_BREAKPOINT_X:
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info->type = XTENSA_BREAKPOINT_EXECUTE;
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break;
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case HW_BREAKPOINT_R:
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info->type = XTENSA_BREAKPOINT_LOAD;
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break;
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case HW_BREAKPOINT_W:
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info->type = XTENSA_BREAKPOINT_STORE;
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break;
|
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case HW_BREAKPOINT_RW:
|
||||
info->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
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break;
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default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Len */
|
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info->len = bp->attr.bp_len;
|
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if (info->len < 1 || info->len > 64 || !is_power_of_2(info->len))
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return -EINVAL;
|
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|
||||
/* Address */
|
||||
info->address = bp->attr.bp_addr;
|
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if (info->address & (info->len - 1))
|
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return -EINVAL;
|
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|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_validate_hwbkpt_settings(struct perf_event *bp)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Build the arch_hw_breakpoint. */
|
||||
ret = arch_build_bp_info(bp);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
|
||||
unsigned long val, void *data)
|
||||
{
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static void xtensa_wsr(unsigned long v, u8 sr)
|
||||
{
|
||||
/* We don't have indexed wsr and creating instruction dynamically
|
||||
* doesn't seem worth it given how small XCHAL_NUM_IBREAK and
|
||||
* XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
|
||||
* the switch below needs to be extended.
|
||||
*/
|
||||
BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
|
||||
BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
|
||||
|
||||
switch (sr) {
|
||||
#if XCHAL_NUM_IBREAK > 0
|
||||
case SREG_IBREAKA + 0:
|
||||
WSR(v, SREG_IBREAKA + 0);
|
||||
break;
|
||||
#endif
|
||||
#if XCHAL_NUM_IBREAK > 1
|
||||
case SREG_IBREAKA + 1:
|
||||
WSR(v, SREG_IBREAKA + 1);
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if XCHAL_NUM_DBREAK > 0
|
||||
case SREG_DBREAKA + 0:
|
||||
WSR(v, SREG_DBREAKA + 0);
|
||||
break;
|
||||
case SREG_DBREAKC + 0:
|
||||
WSR(v, SREG_DBREAKC + 0);
|
||||
break;
|
||||
#endif
|
||||
#if XCHAL_NUM_DBREAK > 1
|
||||
case SREG_DBREAKA + 1:
|
||||
WSR(v, SREG_DBREAKA + 1);
|
||||
break;
|
||||
|
||||
case SREG_DBREAKC + 1:
|
||||
WSR(v, SREG_DBREAKC + 1);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static int alloc_slot(struct perf_event **slot, size_t n,
|
||||
struct perf_event *bp)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; ++i) {
|
||||
if (!slot[i]) {
|
||||
slot[i] = bp;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
static void set_ibreak_regs(int reg, struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
unsigned long ibreakenable;
|
||||
|
||||
xtensa_wsr(info->address, SREG_IBREAKA + reg);
|
||||
RSR(ibreakenable, SREG_IBREAKENABLE);
|
||||
WSR(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
|
||||
}
|
||||
|
||||
static void set_dbreak_regs(int reg, struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
|
||||
|
||||
if (info->type & XTENSA_BREAKPOINT_LOAD)
|
||||
dbreakc |= DBREAKC_LOAD_MASK;
|
||||
if (info->type & XTENSA_BREAKPOINT_STORE)
|
||||
dbreakc |= DBREAKC_STOR_MASK;
|
||||
|
||||
xtensa_wsr(info->address, SREG_DBREAKA + reg);
|
||||
xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
|
||||
}
|
||||
|
||||
int arch_install_hw_breakpoint(struct perf_event *bp)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
|
||||
/* Breakpoint */
|
||||
i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
|
||||
if (i < 0)
|
||||
return i;
|
||||
set_ibreak_regs(i, bp);
|
||||
|
||||
} else {
|
||||
/* Watchpoint */
|
||||
i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
|
||||
if (i < 0)
|
||||
return i;
|
||||
set_dbreak_regs(i, bp);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int free_slot(struct perf_event **slot, size_t n,
|
||||
struct perf_event *bp)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; ++i) {
|
||||
if (slot[i] == bp) {
|
||||
slot[i] = NULL;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
int i;
|
||||
|
||||
if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
|
||||
unsigned long ibreakenable;
|
||||
|
||||
/* Breakpoint */
|
||||
i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
|
||||
if (i >= 0) {
|
||||
RSR(ibreakenable, SREG_IBREAKENABLE);
|
||||
WSR(ibreakenable & ~(1 << i), SREG_IBREAKENABLE);
|
||||
}
|
||||
} else {
|
||||
/* Watchpoint */
|
||||
i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
|
||||
if (i >= 0)
|
||||
xtensa_wsr(0, SREG_DBREAKC + i);
|
||||
}
|
||||
}
|
||||
|
||||
void hw_breakpoint_pmu_read(struct perf_event *bp)
|
||||
{
|
||||
}
|
||||
|
||||
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
|
||||
{
|
||||
int i;
|
||||
struct thread_struct *t = &tsk->thread;
|
||||
|
||||
for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
|
||||
if (t->ptrace_bp[i]) {
|
||||
unregister_hw_breakpoint(t->ptrace_bp[i]);
|
||||
t->ptrace_bp[i] = NULL;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
|
||||
if (t->ptrace_wp[i]) {
|
||||
unregister_hw_breakpoint(t->ptrace_wp[i]);
|
||||
t->ptrace_wp[i] = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Set ptrace breakpoint pointers to zero for this task.
|
||||
* This is required in order to prevent child processes from unregistering
|
||||
* breakpoints held by their parent.
|
||||
*/
|
||||
void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
|
||||
{
|
||||
memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
|
||||
memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
|
||||
}
|
||||
|
||||
void restore_dbreak(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
|
||||
struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
|
||||
|
||||
if (bp)
|
||||
set_dbreak_regs(i, bp);
|
||||
}
|
||||
clear_thread_flag(TIF_DB_DISABLED);
|
||||
}
|
||||
|
||||
int check_hw_breakpoint(struct pt_regs *regs)
|
||||
{
|
||||
if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
|
||||
int i;
|
||||
struct perf_event **bp = this_cpu_ptr(bp_on_reg);
|
||||
|
||||
for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
|
||||
if (bp[i] && !bp[i]->attr.disabled &&
|
||||
regs->pc == bp[i]->attr.bp_addr)
|
||||
perf_bp_event(bp[i], regs);
|
||||
}
|
||||
return 0;
|
||||
} else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
|
||||
struct perf_event **bp = this_cpu_ptr(wp_on_reg);
|
||||
int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
|
||||
DEBUGCAUSE_DBNUM_SHIFT;
|
||||
|
||||
if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
|
||||
if (user_mode(regs)) {
|
||||
perf_bp_event(bp[dbnum], regs);
|
||||
} else {
|
||||
set_thread_flag(TIF_DB_DISABLED);
|
||||
xtensa_wsr(0, SREG_DBREAKC + dbnum);
|
||||
}
|
||||
} else {
|
||||
WARN_ONCE(1,
|
||||
"Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
|
||||
dbnum);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
return -ENOENT;
|
||||
}
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/elf.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/prctl.h>
|
||||
#include <linux/init_task.h>
|
||||
@@ -43,6 +44,7 @@
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/regs.h>
|
||||
#include <asm/hw_breakpoint.h>
|
||||
|
||||
extern void ret_from_fork(void);
|
||||
extern void ret_from_kernel_thread(void);
|
||||
@@ -131,6 +133,7 @@ void flush_thread(void)
|
||||
coprocessor_flush_all(ti);
|
||||
coprocessor_release_all(ti);
|
||||
#endif
|
||||
flush_ptrace_hw_breakpoint(current);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -273,6 +276,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp_thread_fn,
|
||||
ti->cpenable = 0;
|
||||
#endif
|
||||
|
||||
clear_ptrace_hw_breakpoint(p);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -13,21 +13,23 @@
|
||||
* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/security.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/elf.h>
|
||||
#include <asm/coprocessor.h>
|
||||
#include <asm/elf.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
|
||||
void user_enable_single_step(struct task_struct *child)
|
||||
@@ -267,6 +269,146 @@ int ptrace_pokeusr(struct task_struct *child, long regno, long val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
static void ptrace_hbptriggered(struct perf_event *bp,
|
||||
struct perf_sample_data *data,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
int i;
|
||||
siginfo_t info;
|
||||
struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
|
||||
|
||||
if (bp->attr.bp_type & HW_BREAKPOINT_X) {
|
||||
for (i = 0; i < XCHAL_NUM_IBREAK; ++i)
|
||||
if (current->thread.ptrace_bp[i] == bp)
|
||||
break;
|
||||
i <<= 1;
|
||||
} else {
|
||||
for (i = 0; i < XCHAL_NUM_DBREAK; ++i)
|
||||
if (current->thread.ptrace_wp[i] == bp)
|
||||
break;
|
||||
i = (i << 1) | 1;
|
||||
}
|
||||
|
||||
info.si_signo = SIGTRAP;
|
||||
info.si_errno = i;
|
||||
info.si_code = TRAP_HWBKPT;
|
||||
info.si_addr = (void __user *)bkpt->address;
|
||||
|
||||
force_sig_info(SIGTRAP, &info, current);
|
||||
}
|
||||
|
||||
static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
|
||||
{
|
||||
struct perf_event_attr attr;
|
||||
|
||||
ptrace_breakpoint_init(&attr);
|
||||
|
||||
/* Initialise fields to sane defaults. */
|
||||
attr.bp_addr = 0;
|
||||
attr.bp_len = 1;
|
||||
attr.bp_type = type;
|
||||
attr.disabled = 1;
|
||||
|
||||
return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, NULL,
|
||||
tsk);
|
||||
}
|
||||
|
||||
/*
|
||||
* Address bit 0 choose instruction (0) or data (1) break register, bits
|
||||
* 31..1 are the register number.
|
||||
* Both PTRACE_GETHBPREGS and PTRACE_SETHBPREGS transfer two 32-bit words:
|
||||
* address (0) and control (1).
|
||||
* Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set.
|
||||
* Data breakpoint control word bit 31 is 'trigger on store', bit 30 is
|
||||
* 'trigger on load, bits 29..0 are length. Length 0 is used to clear a
|
||||
* breakpoint. To set a breakpoint length must be a power of 2 in the range
|
||||
* 1..64 and the address must be length-aligned.
|
||||
*/
|
||||
|
||||
static long ptrace_gethbpregs(struct task_struct *child, long addr,
|
||||
long __user *datap)
|
||||
{
|
||||
struct perf_event *bp;
|
||||
u32 user_data[2] = {0};
|
||||
bool dbreak = addr & 1;
|
||||
unsigned idx = addr >> 1;
|
||||
|
||||
if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
|
||||
(dbreak && idx >= XCHAL_NUM_DBREAK))
|
||||
return -EINVAL;
|
||||
|
||||
if (dbreak)
|
||||
bp = child->thread.ptrace_wp[idx];
|
||||
else
|
||||
bp = child->thread.ptrace_bp[idx];
|
||||
|
||||
if (bp) {
|
||||
user_data[0] = bp->attr.bp_addr;
|
||||
user_data[1] = bp->attr.disabled ? 0 : bp->attr.bp_len;
|
||||
if (dbreak) {
|
||||
if (bp->attr.bp_type & HW_BREAKPOINT_R)
|
||||
user_data[1] |= DBREAKC_LOAD_MASK;
|
||||
if (bp->attr.bp_type & HW_BREAKPOINT_W)
|
||||
user_data[1] |= DBREAKC_STOR_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
if (copy_to_user(datap, user_data, sizeof(user_data)))
|
||||
return -EFAULT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long ptrace_sethbpregs(struct task_struct *child, long addr,
|
||||
long __user *datap)
|
||||
{
|
||||
struct perf_event *bp;
|
||||
struct perf_event_attr attr;
|
||||
u32 user_data[2];
|
||||
bool dbreak = addr & 1;
|
||||
unsigned idx = addr >> 1;
|
||||
int bp_type = 0;
|
||||
|
||||
if ((!dbreak && idx >= XCHAL_NUM_IBREAK) ||
|
||||
(dbreak && idx >= XCHAL_NUM_DBREAK))
|
||||
return -EINVAL;
|
||||
|
||||
if (copy_from_user(user_data, datap, sizeof(user_data)))
|
||||
return -EFAULT;
|
||||
|
||||
if (dbreak) {
|
||||
bp = child->thread.ptrace_wp[idx];
|
||||
if (user_data[1] & DBREAKC_LOAD_MASK)
|
||||
bp_type |= HW_BREAKPOINT_R;
|
||||
if (user_data[1] & DBREAKC_STOR_MASK)
|
||||
bp_type |= HW_BREAKPOINT_W;
|
||||
} else {
|
||||
bp = child->thread.ptrace_bp[idx];
|
||||
bp_type = HW_BREAKPOINT_X;
|
||||
}
|
||||
|
||||
if (!bp) {
|
||||
bp = ptrace_hbp_create(child,
|
||||
bp_type ? bp_type : HW_BREAKPOINT_RW);
|
||||
if (IS_ERR(bp))
|
||||
return PTR_ERR(bp);
|
||||
if (dbreak)
|
||||
child->thread.ptrace_wp[idx] = bp;
|
||||
else
|
||||
child->thread.ptrace_bp[idx] = bp;
|
||||
}
|
||||
|
||||
attr = bp->attr;
|
||||
attr.bp_addr = user_data[0];
|
||||
attr.bp_len = user_data[1] & ~(DBREAKC_LOAD_MASK | DBREAKC_STOR_MASK);
|
||||
attr.bp_type = bp_type;
|
||||
attr.disabled = !attr.bp_len;
|
||||
|
||||
return modify_user_hw_breakpoint(bp, &attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
long arch_ptrace(struct task_struct *child, long request,
|
||||
unsigned long addr, unsigned long data)
|
||||
{
|
||||
@@ -307,7 +449,15 @@ long arch_ptrace(struct task_struct *child, long request,
|
||||
case PTRACE_SETXTREGS:
|
||||
ret = ptrace_setxregs(child, datap);
|
||||
break;
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
case PTRACE_GETHBPREGS:
|
||||
ret = ptrace_gethbpregs(child, addr, datap);
|
||||
break;
|
||||
|
||||
case PTRACE_SETHBPREGS:
|
||||
ret = ptrace_sethbpregs(child, addr, datap);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ret = ptrace_request(child, request, addr, data);
|
||||
break;
|
||||
|
||||
@@ -39,11 +39,7 @@
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
extern int gdb_enter;
|
||||
extern int return_from_debug_flag;
|
||||
#endif
|
||||
#include <asm/hw_breakpoint.h>
|
||||
|
||||
/*
|
||||
* Machine specific interrupt handlers
|
||||
@@ -162,6 +158,8 @@ COPROCESSOR(7),
|
||||
|
||||
DEFINE_PER_CPU(unsigned long, exc_table[EXC_TABLE_SIZE/4]);
|
||||
|
||||
DEFINE_PER_CPU(struct debug_table, debug_table);
|
||||
|
||||
void die(const char*, struct pt_regs*, long);
|
||||
|
||||
static inline void
|
||||
@@ -205,6 +203,32 @@ extern void do_IRQ(int, struct pt_regs *);
|
||||
|
||||
#if XTENSA_FAKE_NMI
|
||||
|
||||
#define IS_POW2(v) (((v) & ((v) - 1)) == 0)
|
||||
|
||||
#if !(PROFILING_INTLEVEL == XCHAL_EXCM_LEVEL && \
|
||||
IS_POW2(XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL)))
|
||||
#warning "Fake NMI is requested for PMM, but there are other IRQs at or above its level."
|
||||
#warning "Fake NMI will be used, but there will be a bugcheck if one of those IRQs fire."
|
||||
|
||||
static inline void check_valid_nmi(void)
|
||||
{
|
||||
unsigned intread = get_sr(interrupt);
|
||||
unsigned intenable = get_sr(intenable);
|
||||
|
||||
BUG_ON(intread & intenable &
|
||||
~(XTENSA_INTLEVEL_ANDBELOW_MASK(PROFILING_INTLEVEL) ^
|
||||
XTENSA_INTLEVEL_MASK(PROFILING_INTLEVEL) ^
|
||||
BIT(XCHAL_PROFILING_INTERRUPT)));
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void check_valid_nmi(void)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_id);
|
||||
|
||||
DEFINE_PER_CPU(unsigned long, nmi_count);
|
||||
@@ -219,6 +243,7 @@ void do_nmi(struct pt_regs *regs)
|
||||
old_regs = set_irq_regs(regs);
|
||||
nmi_enter();
|
||||
++*this_cpu_ptr(&nmi_count);
|
||||
check_valid_nmi();
|
||||
xtensa_pmu_irq_handler(0, NULL);
|
||||
nmi_exit();
|
||||
set_irq_regs(old_regs);
|
||||
@@ -314,23 +339,22 @@ do_unaligned_user (struct pt_regs *regs)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Handle debug events.
|
||||
* When CONFIG_HAVE_HW_BREAKPOINT is on this handler is called with
|
||||
* preemption disabled to avoid rescheduling and keep mapping of hardware
|
||||
* breakpoint structures to debug registers intact, so that
|
||||
* DEBUGCAUSE.DBNUM could be used in case of data breakpoint hit.
|
||||
*/
|
||||
void
|
||||
do_debug(struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_KGDB
|
||||
/* If remote debugging is configured AND enabled, we give control to
|
||||
* kgdb. Otherwise, we fall through, perhaps giving control to the
|
||||
* native debugger.
|
||||
*/
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
int ret = check_hw_breakpoint(regs);
|
||||
|
||||
if (gdb_enter) {
|
||||
extern void gdb_handle_exception(struct pt_regs *);
|
||||
gdb_handle_exception(regs);
|
||||
return_from_debug_flag = 1;
|
||||
preempt_enable();
|
||||
if (ret == 0)
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
__die_if_kernel("Breakpoint in kernel", regs, SIGKILL);
|
||||
|
||||
/* If in user mode, send SIGTRAP signal to current process */
|
||||
@@ -364,6 +388,15 @@ static void trap_init_excsave(void)
|
||||
__asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1));
|
||||
}
|
||||
|
||||
static void trap_init_debug(void)
|
||||
{
|
||||
unsigned long debugsave = (unsigned long)this_cpu_ptr(&debug_table);
|
||||
|
||||
this_cpu_ptr(&debug_table)->debug_exception = debug_exception;
|
||||
__asm__ __volatile__("wsr %0, excsave" __stringify(XCHAL_DEBUGLEVEL)
|
||||
:: "a"(debugsave));
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize dispatch tables.
|
||||
*
|
||||
@@ -407,12 +440,14 @@ void __init trap_init(void)
|
||||
|
||||
/* Initialize EXCSAVE_1 to hold the address of the exception table. */
|
||||
trap_init_excsave();
|
||||
trap_init_debug();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void secondary_trap_init(void)
|
||||
{
|
||||
trap_init_excsave();
|
||||
trap_init_debug();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -601,7 +601,9 @@ ENDPROC(window_overflow_restore_a0_fixup)
|
||||
|
||||
ENTRY(_DebugInterruptVector)
|
||||
|
||||
xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
|
||||
s32i a0, a3, DT_DEBUG_SAVE
|
||||
l32i a0, a3, DT_DEBUG_EXCEPTION
|
||||
jx a0
|
||||
|
||||
ENDPROC(_DebugInterruptVector)
|
||||
|
||||
مرجع در شماره جدید
Block a user