Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next
* clk-renesas: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock clk: renesas: Mark rza2_cpg_clk_register static clk: renesas: r7s9210: Add USB clocks clk: renesas: r8a77970: Add RPC clocks clk: renesas: r7s9210: Add SDHI clocks * clk-allwinner: clk: sunxi-ng: a64: Allow parent change for VE clock clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock * clk-tegra: clk: tegra: Return the exact clock rate from clk_round_rate clk: tegra30: Use Tegra CPU powergate helper function soc/tegra: pmc: Drop SMP dependency from CPU APIs clk: tegra: Fix maximum audio sync clock for Tegra124/210 clk: tegra: get rid of duplicate defines clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC clk: tegra20: Turn EMC clock gate into divider * clk-meson: (25 commits) clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: Mark some things static clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon ... * clk-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
This commit is contained in:
Stephen Boyd
@@ -128,5 +128,23 @@
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#define CLKID_VDEC_1 153
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#define CLKID_VDEC_HEVC 156
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#define CLKID_GEN_CLK 159
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#define CLKID_VID_PLL 166
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#define CLKID_VCLK 175
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#define CLKID_VCLK2 176
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#define CLKID_VCLK_DIV1 185
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#define CLKID_VCLK_DIV2 186
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#define CLKID_VCLK_DIV4 187
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#define CLKID_VCLK_DIV6 188
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#define CLKID_VCLK_DIV12 189
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#define CLKID_VCLK2_DIV1 190
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#define CLKID_VCLK2_DIV2 191
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#define CLKID_VCLK2_DIV4 192
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#define CLKID_VCLK2_DIV6 193
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#define CLKID_VCLK2_DIV12 194
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#define CLKID_CTS_ENCI 199
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#define CLKID_CTS_ENCP 200
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#define CLKID_CTS_VDAC 201
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#define CLKID_HDMI_TX 202
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#define CLKID_HDMI 205
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#endif /* __GXBB_CLKC_H */
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@@ -103,5 +103,9 @@
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#define CLKID_MPLL1 94
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#define CLKID_MPLL2 95
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#define CLKID_NAND_CLK 112
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#define CLKID_ABP 124
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#define CLKID_PERIPH 126
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#define CLKID_AXI 128
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#define CLKID_L2_DRAM 130
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#endif /* __MESON8B_CLKC_H */
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@@ -50,7 +50,7 @@
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#define R8A7795_CLK_CANFD 39
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#define R8A7795_CLK_HDMI 40
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#define R8A7795_CLK_CSI0 41
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#define R8A7795_CLK_CSIREF 42
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/* CLK_CSIREF was removed */
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#define R8A7795_CLK_CP 43
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#define R8A7795_CLK_CPEX 44
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#define R8A7795_CLK_R 45
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@@ -56,7 +56,7 @@
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#define R8A7796_CLK_CANFD 45
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#define R8A7796_CLK_HDMI 46
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#define R8A7796_CLK_CSI0 47
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#define R8A7796_CLK_CSIREF 48
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/* CLK_CSIREF was removed */
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#define R8A7796_CLK_CP 49
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#define R8A7796_CLK_CPEX 50
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#define R8A7796_CLK_R 51
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@@ -35,8 +35,8 @@
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#define R8A77995_CLK_CRD2 24
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#define R8A77995_CLK_SD0H 25
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#define R8A77995_CLK_SD0 26
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#define R8A77995_CLK_SSP2 27
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#define R8A77995_CLK_SSP1 28
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/* CLK_SSP2 was removed */
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/* CLK_SSP1 was removed */
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#define R8A77995_CLK_RPC 29
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#define R8A77995_CLK_RPCD2 30
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#define R8A77995_CLK_ZA2 31
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@@ -49,5 +49,6 @@
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#define R8A77995_CLK_LV0 38
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#define R8A77995_CLK_LV1 39
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#define R8A77995_CLK_CP 40
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#define R8A77995_CLK_CPEX 41
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#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
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@@ -172,13 +172,14 @@
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#define PCLK_HDCP 232
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#define PCLK_DCF 233
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#define PCLK_SARADC 234
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#define PCLK_ACODECPHY 235
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/* hclk gates */
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#define HCLK_PERI 308
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#define HCLK_TSP 309
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#define HCLK_GMAC 310
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#define HCLK_I2S0_8CH 311
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#define HCLK_I2S1_8CH 313
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#define HCLK_I2S1_8CH 312
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#define HCLK_I2S2_2CH 313
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#define HCLK_SPDIF_8CH 314
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#define HCLK_VOP 315
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@@ -15,4 +15,7 @@
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#define CLK_MIXER1 7
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#define CLK_WB 8
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#define CLK_BUS_ROT 9
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#define CLK_ROT 10
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#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
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70
include/dt-bindings/clock/suniv-ccu-f1c100s.h
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70
include/dt-bindings/clock/suniv-ccu-f1c100s.h
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@@ -0,0 +1,70 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*
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* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
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*
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*/
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#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
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#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
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#define CLK_CPU 11
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#define CLK_BUS_DMA 14
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#define CLK_BUS_MMC0 15
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#define CLK_BUS_MMC1 16
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#define CLK_BUS_DRAM 17
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#define CLK_BUS_SPI0 18
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#define CLK_BUS_SPI1 19
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#define CLK_BUS_OTG 20
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#define CLK_BUS_VE 21
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#define CLK_BUS_LCD 22
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#define CLK_BUS_DEINTERLACE 23
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#define CLK_BUS_CSI 24
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#define CLK_BUS_TVD 25
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#define CLK_BUS_TVE 26
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#define CLK_BUS_DE_BE 27
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#define CLK_BUS_DE_FE 28
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#define CLK_BUS_CODEC 29
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#define CLK_BUS_SPDIF 30
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#define CLK_BUS_IR 31
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#define CLK_BUS_RSB 32
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#define CLK_BUS_I2S0 33
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#define CLK_BUS_I2C0 34
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#define CLK_BUS_I2C1 35
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#define CLK_BUS_I2C2 36
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#define CLK_BUS_PIO 37
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#define CLK_BUS_UART0 38
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#define CLK_BUS_UART1 39
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#define CLK_BUS_UART2 40
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#define CLK_MMC0 41
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#define CLK_MMC0_SAMPLE 42
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#define CLK_MMC0_OUTPUT 43
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#define CLK_MMC1 44
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#define CLK_MMC1_SAMPLE 45
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#define CLK_MMC1_OUTPUT 46
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#define CLK_I2S 47
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#define CLK_SPDIF 48
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#define CLK_USB_PHY0 49
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#define CLK_DRAM_VE 50
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#define CLK_DRAM_CSI 51
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#define CLK_DRAM_DEINTERLACE 52
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#define CLK_DRAM_TVD 53
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#define CLK_DRAM_DE_FE 54
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#define CLK_DRAM_DE_BE 55
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#define CLK_DE_BE 56
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#define CLK_DE_FE 57
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#define CLK_TCON 58
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#define CLK_DEINTERLACE 59
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#define CLK_TVE2_CLK 60
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#define CLK_TVE1_CLK 61
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#define CLK_TVD 62
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#define CLK_CSI 63
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#define CLK_VE 64
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#define CLK_CODEC 65
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#define CLK_AVS 66
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#endif
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