[MIPS] DDB5477: Remove support
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
committed by
Ralf Baechle
Ralf Baechle
parent
796756bab6
commit
ff32b062ea
@@ -19,7 +19,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
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# These are still pretty much in the old state, watch, go blind.
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#
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obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
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obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
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obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
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obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
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obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
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@@ -1,78 +0,0 @@
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* Board specific pci fixups.
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*
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* Copyright 2001, 2002, 2003 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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static void ddb5477_fixup(struct pci_dev *dev)
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{
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u8 old;
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printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n");
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pci_read_config_byte(dev, 0x41, &old);
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pci_write_config_byte(dev, 0x41, old | 0xd0);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533,
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ddb5477_fixup);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535,
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ddb5477_fixup);
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/*
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* Fixup baseboard AMD chip so that tx does not underflow.
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* bcr_18 |= 0x0800
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* This sets NOUFLO bit which makes tx not start until whole pkt
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* is fetched to the chip.
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*/
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#define PCNET32_WIO_RDP 0x10
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#define PCNET32_WIO_RAP 0x12
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#define PCNET32_WIO_RESET 0x14
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#define PCNET32_WIO_BDP 0x16
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static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
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{
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unsigned long ioaddr;
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u16 temp;
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ioaddr = pci_resource_start(dev, 0);
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inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
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/* bcr_18 |= 0x0800 */
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outw(18, ioaddr + PCNET32_WIO_RAP);
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temp = inw(ioaddr + PCNET32_WIO_BDP);
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temp |= 0x0800;
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outw(18, ioaddr + PCNET32_WIO_RAP);
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outw(temp, ioaddr + PCNET32_WIO_BDP);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
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ddb5477_amd_lance_fixup);
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@@ -1,278 +0,0 @@
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/***********************************************************************
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* arch/mips/ddb5xxx/ddb5477/pci_ops.c
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* Define the pci_ops for DB5477.
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*
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* Much of the code is derived from the original DDB5074 port by
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* Geert Uytterhoeven <geert@sonycom.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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***********************************************************************
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*/
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/*
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* DDB5477 has two PCI channels, external PCI and IOPIC (internal)
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* Therefore we provide two sets of pci_ops.
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*/
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/debug.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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/*
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* config_swap structure records what set of pdar/pmr are used
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* to access pci config space. It also provides a place hold the
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* original values for future restoring.
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*/
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struct pci_config_swap {
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u32 pdar;
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u32 pmr;
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u32 config_base;
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u32 config_size;
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u32 pdar_backup;
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u32 pmr_backup;
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};
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/*
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* On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
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*/
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struct pci_config_swap ext_pci_swap = {
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DDB_PCIW0,
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DDB_PCIINIT00,
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DDB_PCI0_CONFIG_BASE,
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DDB_PCI0_CONFIG_SIZE
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};
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struct pci_config_swap io_pci_swap = {
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DDB_IOPCIW0,
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DDB_PCIINIT01,
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DDB_PCI1_CONFIG_BASE,
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DDB_PCI1_CONFIG_SIZE
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};
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/*
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* access config space
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*/
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static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
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u32 slot_num)
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{
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u32 pci_addr = 0;
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u32 pciinit_offset = 0;
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u32 virt_addr;
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u32 option;
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/* minimum pdar (window) size is 2MB */
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db_assert(swap->config_size >= (2 << 20));
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db_assert(slot_num < (1 << 5));
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db_assert(bus < (1 << 8));
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/* backup registers */
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swap->pdar_backup = ddb_in32(swap->pdar);
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swap->pmr_backup = ddb_in32(swap->pmr);
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/* set the pdar (pci window) register */
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ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
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0, /* not on local memory bus */
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0); /* not visible from PCI bus (N/A) */
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/*
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* calcuate the absolute pci config addr;
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* according to the spec, we start scanning from adr:11 (0x800)
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*/
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if (bus == 0) {
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/* type 0 config */
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pci_addr = 0x800 << slot_num;
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} else {
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/* type 1 config */
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pci_addr = (bus << 16) | (slot_num << 11);
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}
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/*
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* if pci_addr is less than pci config window size, we set
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* pciinit_offset to 0 and adjust the virt_address.
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* Otherwise we will try to adjust pciinit_offset.
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*/
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if (pci_addr < swap->config_size) {
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virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
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pciinit_offset = 0;
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} else {
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db_assert((pci_addr & (swap->config_size - 1)) == 0);
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virt_addr = KSEG1ADDR(swap->config_base);
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pciinit_offset = pci_addr;
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}
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/* set the pmr register */
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option = DDB_PCI_ACCESS_32;
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if (bus != 0)
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option |= DDB_PCI_CFGTYPE1;
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ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
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return virt_addr;
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}
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static inline void ddb_close_config_base(struct pci_config_swap *swap)
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{
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ddb_out32(swap->pdar, swap->pdar_backup);
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ddb_out32(swap->pmr, swap->pmr_backup);
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}
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static int read_config_dword(struct pci_config_swap *swap,
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struct pci_bus *bus, u32 devfn, u32 where,
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u32 * val)
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{
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u32 bus_num, slot_num, func_num;
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u32 base;
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db_assert((where & 3) == 0);
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db_assert(where < (1 << 8));
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/* check if the bus is top-level */
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if (bus->parent != NULL) {
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bus_num = bus->number;
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db_assert(bus_num != 0);
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} else {
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bus_num = 0;
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}
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slot_num = PCI_SLOT(devfn);
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func_num = PCI_FUNC(devfn);
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base = ddb_access_config_base(swap, bus_num, slot_num);
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*val = *(volatile u32 *) (base + (func_num << 8) + where);
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ddb_close_config_base(swap);
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return PCIBIOS_SUCCESSFUL;
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}
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static int read_config_word(struct pci_config_swap *swap,
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struct pci_bus *bus, u32 devfn, u32 where,
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u16 * val)
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{
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int status;
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u32 result;
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db_assert((where & 1) == 0);
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status = read_config_dword(swap, bus, devfn, where & ~3, &result);
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if (where & 2)
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result >>= 16;
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*val = result & 0xffff;
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return status;
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}
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static int read_config_byte(struct pci_config_swap *swap,
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struct pci_bus *bus, u32 devfn, u32 where,
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u8 * val)
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{
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int status;
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u32 result;
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status = read_config_dword(swap, bus, devfn, where & ~3, &result);
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if (where & 1)
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result >>= 8;
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if (where & 2)
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result >>= 16;
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*val = result & 0xff;
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return status;
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}
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static int write_config_dword(struct pci_config_swap *swap,
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struct pci_bus *bus, u32 devfn, u32 where,
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u32 val)
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{
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u32 bus_num, slot_num, func_num;
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u32 base;
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db_assert((where & 3) == 0);
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db_assert(where < (1 << 8));
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/* check if the bus is top-level */
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if (bus->parent != NULL) {
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bus_num = bus->number;
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db_assert(bus_num != 0);
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} else {
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bus_num = 0;
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}
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slot_num = PCI_SLOT(devfn);
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func_num = PCI_FUNC(devfn);
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base = ddb_access_config_base(swap, bus_num, slot_num);
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*(volatile u32 *) (base + (func_num << 8) + where) = val;
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ddb_close_config_base(swap);
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return PCIBIOS_SUCCESSFUL;
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}
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static int write_config_word(struct pci_config_swap *swap,
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struct pci_bus *bus, u32 devfn, u32 where, u16 val)
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{
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int status, shift = 0;
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u32 result;
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db_assert((where & 1) == 0);
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status = read_config_dword(swap, bus, devfn, where & ~3, &result);
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if (status != PCIBIOS_SUCCESSFUL)
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return status;
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if (where & 2)
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shift += 16;
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result &= ~(0xffff << shift);
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result |= val << shift;
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return write_config_dword(swap, bus, devfn, where & ~3, result);
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}
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static int write_config_byte(struct pci_config_swap *swap,
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struct pci_bus *bus, u32 devfn, u32 where, u8 val)
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{
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int status, shift = 0;
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u32 result;
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status = read_config_dword(swap, bus, devfn, where & ~3, &result);
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if (status != PCIBIOS_SUCCESSFUL)
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return status;
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if (where & 2)
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shift += 16;
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if (where & 1)
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shift += 8;
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result &= ~(0xff << shift);
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result |= val << shift;
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return write_config_dword(swap, bus, devfn, where & ~3, result);
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}
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#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \
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static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \
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{ \
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if (size == 1) \
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return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
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else if (size == 2) \
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return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
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/* Size must be 4 */ \
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return rw##_config_dword(pciswap, bus, devfn, where, val); \
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}
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MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *)
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MAKE_PCI_OPS(extpci, write, &ext_pci_swap,)
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MAKE_PCI_OPS(iopci, read, &io_pci_swap, *)
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MAKE_PCI_OPS(iopci, write, &io_pci_swap,)
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struct pci_ops ddb5477_ext_pci_ops = {
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.read = extpci_read_config,
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.write = extpci_write_config
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};
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struct pci_ops ddb5477_io_pci_ops = {
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.read = iopci_read_config,
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.write = iopci_write_config
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};
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@@ -1,207 +0,0 @@
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/*
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* PCI code for DDB5477.
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*
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* Copyright (C) 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/bootinfo.h>
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#include <asm/debug.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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static struct resource extpci_io_resource = {
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.start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
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.end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
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.name = "ext pci IO space",
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.flags = IORESOURCE_IO
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};
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static struct resource extpci_mem_resource = {
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.start = DDB_PCI0_MEM_BASE + 0x100000,
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.end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
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.name = "ext pci memory space",
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.flags = IORESOURCE_MEM
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};
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static struct resource iopci_io_resource = {
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.start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
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.end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
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.name = "io pci IO space",
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.flags = IORESOURCE_IO
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};
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static struct resource iopci_mem_resource = {
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.start = DDB_PCI1_MEM_BASE,
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.end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
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.name = "ext pci memory space",
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.flags = IORESOURCE_MEM
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};
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extern struct pci_ops ddb5477_ext_pci_ops;
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extern struct pci_ops ddb5477_io_pci_ops;
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struct pci_controller ddb5477_ext_controller = {
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.pci_ops = &ddb5477_ext_pci_ops,
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.io_resource = &extpci_io_resource,
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.mem_resource = &extpci_mem_resource
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};
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struct pci_controller ddb5477_io_controller = {
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.pci_ops = &ddb5477_io_pci_ops,
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.io_resource = &iopci_io_resource,
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.mem_resource = &iopci_mem_resource
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};
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/*
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* we fix up irqs based on the slot number.
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* The first entry is at AD:11.
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* Fortunately this works because, although we have two pci buses,
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* they all have different slot numbers (except for rockhopper slot 20
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* which is handled below).
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*
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*/
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/*
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* irq mapping : device -> pci int # -> vrc4377 irq# ,
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* ddb5477 board manual page 4 and vrc5477 manual page 46
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*/
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/*
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* based on ddb5477 manual page 11
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*/
|
||||
#define MAX_SLOT_NUM 21
|
||||
static unsigned char irq_map[MAX_SLOT_NUM] = {
|
||||
/* SLOT: 0, AD:11 */ 0xff,
|
||||
/* SLOT: 1, AD:12 */ 0xff,
|
||||
/* SLOT: 2, AD:13 */ 0xff,
|
||||
/* SLOT: 3, AD:14 */ 0xff,
|
||||
/* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
|
||||
/* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
|
||||
/* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
|
||||
/* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
|
||||
/* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
|
||||
/* SLOT: 9, AD:20 */ 0xff,
|
||||
/* SLOT: 10, AD:21 */ 0xff,
|
||||
/* SLOT: 11, AD:22 */ 0xff,
|
||||
/* SLOT: 12, AD:23 */ 0xff,
|
||||
/* SLOT: 13, AD:24 */ 0xff,
|
||||
/* SLOT: 14, AD:25 */ 0xff,
|
||||
/* SLOT: 15, AD:26 */ 0xff,
|
||||
/* SLOT: 16, AD:27 */ 0xff,
|
||||
/* SLOT: 17, AD:28 */ 0xff,
|
||||
/* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
|
||||
/* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
|
||||
/* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
|
||||
};
|
||||
static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
|
||||
/* SLOT: 0, AD:11 */ 0xff,
|
||||
/* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
|
||||
/* SLOT: 2, AD:13 */ 0xff,
|
||||
/* SLOT: 3, AD:14 */ 0xff,
|
||||
/* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */
|
||||
/* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
|
||||
/* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
|
||||
/* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
|
||||
/* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */
|
||||
/* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
|
||||
/* SLOT: 10, AD:21 */ 0xff,
|
||||
/* SLOT: 11, AD:22 */ 0xff,
|
||||
/* SLOT: 12, AD:23 */ 0xff,
|
||||
/* SLOT: 13, AD:24 */ 0xff,
|
||||
/* SLOT: 14, AD:25 */ 0xff,
|
||||
/* SLOT: 15, AD:26 */ 0xff,
|
||||
/* SLOT: 16, AD:27 */ 0xff,
|
||||
/* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
|
||||
/* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
|
||||
/* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
|
||||
/* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
|
||||
};
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int slot_num;
|
||||
unsigned char *slot_irq_map;
|
||||
unsigned char irq;
|
||||
|
||||
/*
|
||||
* We ignore the swizzled slot and pin values. The original
|
||||
* pci_fixup_irq() codes largely base irq number on the dev slot
|
||||
* numbers because except for one case they are unique even
|
||||
* though there are multiple pci buses.
|
||||
*/
|
||||
|
||||
if (mips_machtype == MACH_NEC_ROCKHOPPERII)
|
||||
slot_irq_map = rockhopperII_irq_map;
|
||||
else
|
||||
slot_irq_map = irq_map;
|
||||
|
||||
slot_num = PCI_SLOT(dev->devfn);
|
||||
irq = slot_irq_map[slot_num];
|
||||
|
||||
db_assert(slot_num < MAX_SLOT_NUM);
|
||||
|
||||
db_assert(irq != 0xff);
|
||||
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
|
||||
|
||||
if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
|
||||
/* hack to distinquish overlapping slot 20s, one
|
||||
* on bus 0 (ALI USB on the M1535 on the backplane),
|
||||
* and one on bus 2 (NEC USB controller on the CPU board)
|
||||
* Make the M1535 USB - ISA IRQ number 9.
|
||||
*/
|
||||
if (slot_num == 20 && dev->bus->number == 0) {
|
||||
pci_write_config_byte(dev,
|
||||
PCI_INTERRUPT_LINE,
|
||||
9);
|
||||
irq = 9;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
/* Do platform specific device initialization at pci_enable_device() time */
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ddb_pci_reset_bus(void)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
/*
|
||||
* I am not sure about the "official" procedure, the following
|
||||
* steps work as far as I know:
|
||||
* We first set PCI cold reset bit (bit 31) in PCICTRL-H.
|
||||
* Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
|
||||
* The same is true for both PCI channels.
|
||||
*/
|
||||
temp = ddb_in32(DDB_PCICTL0_H);
|
||||
temp |= 0x80000000;
|
||||
ddb_out32(DDB_PCICTL0_H, temp);
|
||||
temp &= ~0xc0000000;
|
||||
ddb_out32(DDB_PCICTL0_H, temp);
|
||||
|
||||
temp = ddb_in32(DDB_PCICTL1_H);
|
||||
temp |= 0x80000000;
|
||||
ddb_out32(DDB_PCICTL1_H, temp);
|
||||
temp &= ~0xc0000000;
|
||||
ddb_out32(DDB_PCICTL1_H, temp);
|
||||
}
|
||||
Reference in New Issue
Block a user