Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "This is a largeish batch of fixes, mostly because I missed -rc2 due to travel/vacation. So in number these are a bit more than ideal unless you amortize them over two -rcs. Quick breakdown: - Defconfig updates - Making multi_v7_defconfig useful on more hardware to encourage single-image usage - Davinci and nomadik updates due to new code merged this merge window - Fixes for UART on Samsung platforms, both PM and clock-related - A handful of warning fixes from defconfig builds, including for max8925 backlight and pxamci (both with appropriate acks) - Exynos5440 fixes for LPAE configuration, PM - ...plus a bunch of other smaller changes all over the place I expect to switch to regressions-or-severe-bugs-only fixes from here on out" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits) mfd: max8925: fix dt code for backlight ARM: omap5: Only select errata 798181 if SMP ARM: EXYNOS: Update CONFIG_ARCH_NR_GPIO for Exynos ARM: EXYNOS: Fix low level debug support ARM: SAMSUNG: Save/restore only selected uart's registers ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm ARM: S3C24XX: Add missing clkdev entries for s3c2440 UART ARM: multi_v7_defconfig: Select USB chipidea driver ARM: pxa: propagate errors from regulator_enable() to pxamci ARM: zynq: fix compilation warning ARM: keystone: fix compilation warning ARM: highbank: Only touch common coherency control register fields ARM: footbridge: fix overlapping PCI mappings dmaengine: shdma: fix a build failure on platforms with no DMA support ARM: STi: Set correct ARM ERRATAs. ARM: dts: STi: Fix pinconf setup for STiH416 serial2 ARM: nomadik: configure for NO_HZ and HRTIMERS ARM: nomadik: update defconfig base ARM: nomadik: Update MMC defconfigs ARM: davinci: defconfig: enable EDMA driver ...
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@@ -103,15 +103,15 @@
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#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
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#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
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#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
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#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
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#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
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#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
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#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
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#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
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#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
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#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
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#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
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#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
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#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
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