Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpu updates from Ingo Molnar: "The main changes in this cycle were: - Add support for the "Dhyana" x86 CPUs by Hygon: these are licensed based on the AMD Zen architecture, and are built and sold in China, for domestic datacenter use. The code is pretty close to AMD support, mostly with a few quirks and enumeration differences. (Pu Wen) - Enable CPUID support on Cyrix 6x86/6x86L processors" * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: tools/cpupower: Add Hygon Dhyana support cpufreq: Add Hygon Dhyana support ACPI: Add Hygon Dhyana support x86/xen: Add Hygon Dhyana support to Xen x86/kvm: Add Hygon Dhyana support to KVM x86/mce: Add Hygon Dhyana support to the MCA infrastructure x86/bugs: Add Hygon Dhyana to the respective mitigation machinery x86/apic: Add Hygon Dhyana support x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge x86/amd_nb: Check vendor in AMD-only functions x86/alternative: Init ideal_nops for Hygon Dhyana x86/events: Add Hygon Dhyana support to PMU infrastructure x86/smpboot: Do not use BSP INIT delay and MWAIT to idle on Dhyana x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana x86/cpu: Create Hygon Dhyana architecture support file x86/CPU: Change query logic so CPUID is enabled before testing x86/CPU: Use correct macros for Cyrix calls
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@@ -103,6 +103,9 @@ static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
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static inline bool amd_gart_present(void)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return false;
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/* GART present only on Fam15h, upto model 0fh */
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
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(boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
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@@ -3,5 +3,6 @@
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#define _ASM_X86_CACHEINFO_H
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void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
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void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
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#endif /* _ASM_X86_CACHEINFO_H */
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@@ -364,6 +364,10 @@ struct x86_emulate_ctxt {
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#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx 0x21726574
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#define X86EMUL_CPUID_VENDOR_AMDisbetterI_edx 0x74656273
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#define X86EMUL_CPUID_VENDOR_HygonGenuine_ebx 0x6f677948
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#define X86EMUL_CPUID_VENDOR_HygonGenuine_ecx 0x656e6975
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#define X86EMUL_CPUID_VENDOR_HygonGenuine_edx 0x6e65476e
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#define X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 0x756e6547
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#define X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 0x6c65746e
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#define X86EMUL_CPUID_VENDOR_GenuineIntel_edx 0x49656e69
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@@ -217,6 +217,8 @@ static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
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#endif
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static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
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int mce_available(struct cpuinfo_x86 *c);
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bool mce_is_memory_error(struct mce *m);
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@@ -155,7 +155,8 @@ enum cpuid_regs_idx {
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_HYGON 9
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#define X86_VENDOR_NUM 10
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#define X86_VENDOR_UNKNOWN 0xff
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@@ -83,9 +83,10 @@ static inline void cpu_emergency_vmxoff(void)
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*/
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static inline int cpu_has_svm(const char **msg)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
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boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) {
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if (msg)
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*msg = "not amd";
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*msg = "not amd or hygon";
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return 0;
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}
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