Merge tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"It is pretty calm and chill in pin control for the moment. Just
incremental development.
There is an odd patch to the Super-H architecture, it's coming from
the maintainers so should be fine.
Summary:
New drivers:
- Bitmain BM1880 pin controller
- Mediatek MT8516
- Cirrus Logich Lochnagar PMIC pins
Updates:
- Incremental development on Renesas SH-PFC
- Incremental development on Intel pin controller and some particular
updates for Cedarfork.
- Pin configuration support in Allwinner SunXi drivers
- Suspend/resume support in the NXP/Freescale i.MX8MQ driver
- Support for more packaging of the ST Micro STM32"
* tag 'pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: mcp23s08: Do not complain about unsupported params
pinctrl: Rework Kconfig dependency for BM1880 pinctrl driver
MAINTAINERS: Add entry for BM1880 pinctrl
pinctrl: Add pinctrl support for BM1880 SoC
dt-bindings: pinctrl: Add BM1880 pinctrl binding
pinctrl: stm32: check irq controller availability at probe
pinctrl: mediatek: Add MT8516 Pinctrl driver
pinctrl: zte: fix leaked of_node references
pinctrl: intel: Increase readability of intel_gpio_update_pad_mode()
pinctrl: intel: Retain HOSTSW_OWN for requested gpio pin
pinctrl: pistachio: fix leaked of_node references
pinctrl: sunxi: Support I/O bias voltage setting on H6
pinctrl: sunxi: Prepare for alternative bias voltage setting methods
pinctrl: st: fix leaked of_node references
pinctrl: samsung: fix leaked of_node references
pinctrl: stm32: align stm32mp157 pin names
pinctrl: stm32: add package information for stm32mp157c
pinctrl: stm32: introduce package support
dt-bindings: pinctrl: stm32: add new entry for package information
pinctrl: imx8mq: Add suspend/resume ops
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,98 @@
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Bitmain BM1880 Pin Controller
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This binding describes the pin controller found in the BM1880 SoC.
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Required Properties:
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- compatible: Should be "bitmain,bm1880-pinctrl"
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- reg: Offset and length of pinctrl space in SCTRL.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
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includes only pinmux as there is no pinconf support available in SoC.
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Each configuration node can consist of multiple nodes describing the pinmux
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options. The name of each subnode is not important; all subnodes should be
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enumerated and processed purely based on their content.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pinmux subnode:
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Required Properties:
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- pins: An array of strings, each string containing the name of a pin.
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Valid values for pins are:
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MIO0 - MIO111
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- groups: An array of strings, each string containing the name of a pin
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group. Valid values for groups are:
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nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp,
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pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp,
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pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp,
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pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp,
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pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp,
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pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp,
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pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp,
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pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp,
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i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp,
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uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp,
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uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp,
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uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp,
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gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp,
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gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp,
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gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp,
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gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp,
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gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp,
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gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp,
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gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp,
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gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp,
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gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp,
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gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp,
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gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp,
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gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp,
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gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp,
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gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp,
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i2s1_grp, i2s1_mclkin_grp, spi0_grp
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- function: An array of strings, each string containing the name of the
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pinmux functions. The following are the list of pinmux
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functions available:
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nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4,
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pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13,
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pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22,
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pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31,
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pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3,
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i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7,
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uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15,
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gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8,
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gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16,
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gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
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gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
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gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
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gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
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gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51,
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gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58,
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gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65,
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gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
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spi0
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Example:
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pinctrl: pinctrl@50 {
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compatible = "bitmain,bm1880-pinctrl";
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reg = <0x50 0x4B0>;
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pinctrl_uart0_default: uart0-default {
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pinmux {
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groups = "uart0_grp";
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function = "uart0";
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};
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};
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};
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141
Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt
Normal file
141
Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.txt
Normal file
@@ -0,0 +1,141 @@
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Cirrus Logic Lochnagar Audio Development Board
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Lochnagar is an evaluation and development board for Cirrus Logic
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Smart CODEC and Amp devices. It allows the connection of most Cirrus
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Logic devices on mini-cards, as well as allowing connection of
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various application processor systems to provide a full evaluation
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platform. Audio system topology, clocking and power can all be
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controlled through the Lochnagar, allowing the device under test
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to be used in a variety of possible use cases.
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This binding document describes the binding for the pinctrl portion
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of the driver.
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Also see these documents for generic binding information:
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[1] GPIO : ../gpio/gpio.txt
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[2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
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And these for relevant defines:
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[3] include/dt-bindings/pinctrl/lochnagar.h
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This binding must be part of the Lochnagar MFD binding:
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[4] ../mfd/cirrus,lochnagar.txt
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Required properties:
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- compatible : One of the following strings:
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"cirrus,lochnagar-pinctrl"
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- gpio-controller : Indicates this device is a GPIO controller.
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- #gpio-cells : Must be 2. The first cell is the pin number, see
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[3] for available pins and the second cell is used to specify
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optional parameters, see [1].
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- gpio-ranges : Range of pins managed by the GPIO controller, see
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[1]. Both the GPIO and Pinctrl base should be set to zero and the
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count to the appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define,
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see [3].
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- pinctrl-names : A pinctrl state named "default" must be defined.
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- pinctrl-0 : A phandle to the default pinctrl state.
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Required sub-nodes:
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The pin configurations are defined as a child of the pinctrl states
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node, see [2]. Each sub-node can have the following properties:
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- groups : A list of groups to select (either this or "pins" must be
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specified), available groups:
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codec-aif1, codec-aif2, codec-aif3, dsp-aif1, dsp-aif2, psia1,
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psia2, gf-aif1, gf-aif2, gf-aif3, gf-aif4, spdif-aif, usb-aif1,
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usb-aif2, adat-aif, soundcard-aif
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- pins : A list of pin names to select (either this or "groups" must
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be specified), available pins:
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fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5,
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fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4,
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codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1,
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dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2,
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gf-gpio3, gf-gpio7, codec-aif1-bclk, codec-aif1-rxdat,
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codec-aif1-lrclk, codec-aif1-txdat, codec-aif2-bclk,
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codec-aif2-rxdat, codec-aif2-lrclk, codec-aif2-txdat,
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codec-aif3-bclk, codec-aif3-rxdat, codec-aif3-lrclk,
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codec-aif3-txdat, dsp-aif1-bclk, dsp-aif1-rxdat, dsp-aif1-lrclk,
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dsp-aif1-txdat, dsp-aif2-bclk, dsp-aif2-rxdat,
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dsp-aif2-lrclk, dsp-aif2-txdat, psia1-bclk, psia1-rxdat,
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psia1-lrclk, psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
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psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat, gf-aif3-lrclk,
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gf-aif3-txdat, gf-aif4-bclk, gf-aif4-rxdat, gf-aif4-lrclk,
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gf-aif4-txdat, gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
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gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat, gf-aif2-lrclk,
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gf-aif2-txdat, dsp-uart1-rx, dsp-uart1-tx, dsp-uart2-rx,
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dsp-uart2-tx, gf-uart2-rx, gf-uart2-tx, usb-uart-rx,
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codec-pdmclk1, codec-pdmdat1, codec-pdmclk2, codec-pdmdat2,
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codec-dmicclk1, codec-dmicdat1, codec-dmicclk2, codec-dmicdat2,
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codec-dmicclk3, codec-dmicdat3, codec-dmicclk4, codec-dmicdat4,
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dsp-dmicclk1, dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl,
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i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, dsp-standby,
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codec-mclk1, codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk,
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gf-gpio1, gf-gpio5, dsp-gpio20, led1, led2
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- function : The mux function to select, available functions:
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aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5,
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fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4,
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codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1,
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dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2,
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gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5, dsp-gpio20, codec-clkout,
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dsp-clkout, pmic-32k, spdif-clkout, clk-12m288, clk-11m2986,
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clk-24m576, clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1,
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gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1, codec-mclk2,
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dsp-clkin, psia1-mclk, psia2-mclk, spdif-mclk, codec-irq,
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codec-reset, dsp-reset, dsp-irq, dsp-standby, codec-pdmclk1,
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codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, codec-dmicclk1,
|
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codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, codec-dmicclk3,
|
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codec-dmicdat3, codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1,
|
||||
dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx,
|
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dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, gf-uart2-rx,
|
||||
gf-uart2-tx, usb-uart-rx, usb-uart-tx, i2c2-scl, i2c2-sda,
|
||||
i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, spdif-aif, psia1,
|
||||
psia1-bclk, psia1-lrclk, psia1-rxdat, psia1-txdat, psia2,
|
||||
psia2-bclk, psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1,
|
||||
codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat,
|
||||
codec-aif1-txdat, codec-aif2, codec-aif2-bclk, codec-aif2-lrclk,
|
||||
codec-aif2-rxdat, codec-aif2-txdat, codec-aif3, codec-aif3-bclk,
|
||||
codec-aif3-lrclk, codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1,
|
||||
dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat, dsp-aif1-txdat,
|
||||
dsp-aif2, dsp-aif2-bclk, dsp-aif2-lrclk, dsp-aif2-rxdat,
|
||||
dsp-aif2-txdat, gf-aif3, gf-aif3-bclk, gf-aif3-lrclk,
|
||||
gf-aif3-rxdat, gf-aif3-txdat, gf-aif4, gf-aif4-bclk,
|
||||
gf-aif4-lrclk, gf-aif4-rxdat, gf-aif4-txdat, gf-aif1,
|
||||
gf-aif1-bclk, gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat,
|
||||
gf-aif2, gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat,
|
||||
gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif, soundcard-aif,
|
||||
|
||||
- output-enable : Specifies that an AIF group will be used as a master
|
||||
interface (either this or input-enable is required if a group is
|
||||
being muxed to an AIF)
|
||||
- input-enable : Specifies that an AIF group will be used as a slave
|
||||
interface (either this or output-enable is required if a group is
|
||||
being muxed to an AIF)
|
||||
|
||||
Example:
|
||||
|
||||
lochnagar-pinctrl {
|
||||
compatible = "cirrus,lochnagar-pinctrl";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pin-settings>;
|
||||
|
||||
pin-settings: pin-settings {
|
||||
ap-aif {
|
||||
input-enable;
|
||||
groups = "gf-aif1";
|
||||
function = "codec-aif3";
|
||||
};
|
||||
codec-aif {
|
||||
output-enable;
|
||||
groups = "codec-aif3";
|
||||
function = "gf-aif1";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -48,9 +48,9 @@ PAD_CTL_HYS (1 << 3)
|
||||
PAD_CTL_SRE_SLOW (1 << 2)
|
||||
PAD_CTL_SRE_FAST (0 << 2)
|
||||
PAD_CTL_DSE_X1 (0 << 0)
|
||||
PAD_CTL_DSE_X2 (1 << 0)
|
||||
PAD_CTL_DSE_X3 (2 << 0)
|
||||
PAD_CTL_DSE_X4 (3 << 0)
|
||||
PAD_CTL_DSE_X4 (1 << 0)
|
||||
PAD_CTL_DSE_X2 (2 << 0)
|
||||
PAD_CTL_DSE_X6 (3 << 0)
|
||||
|
||||
Examples:
|
||||
While iomuxc-lpsr is intended to be used by dedicated peripherals to take
|
||||
|
||||
@@ -11,6 +11,7 @@ Required properties:
|
||||
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
|
||||
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
|
||||
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
|
||||
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
|
||||
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
|
||||
specify pins.
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
|
||||
132
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
Normal file
132
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
Normal file
@@ -0,0 +1,132 @@
|
||||
* Mediatek MT8183 Pin Controller
|
||||
|
||||
The Mediatek's Pin controller is used to control SoC pins.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be one of the following.
|
||||
"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See the below
|
||||
mentioned gpio binding representation for description of particular cells.
|
||||
- gpio-ranges : gpio valid number range.
|
||||
- reg: physical address base for gpio base registers. There are 10 GPIO
|
||||
physical address base in mt8183.
|
||||
|
||||
Optional properties:
|
||||
- reg-names: gpio base register names. There are 10 gpio base register
|
||||
names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
|
||||
"iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint".
|
||||
- interrupt-controller: Marks the device node as an interrupt controller
|
||||
- #interrupt-cells: Should be two.
|
||||
- interrupts : The interrupt outputs to sysirq.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices.
|
||||
|
||||
Subnode format
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input schmitt.
|
||||
|
||||
node {
|
||||
pinmux = <PIN_NUMBER_PINMUX>;
|
||||
GENERIC_PINCONFIG;
|
||||
};
|
||||
|
||||
Required properties:
|
||||
- pinmux: integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are defined
|
||||
as macros in boot/dts/<soc>-pinfunc.h directly.
|
||||
|
||||
Optional properties:
|
||||
- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
|
||||
bias-pull-down, bias-pull-up, input-enable, input-disable, output-low,
|
||||
output-high, input-schmitt-enable, input-schmitt-disable
|
||||
and drive-strength are valid.
|
||||
|
||||
Some special pins have extra pull up strength, there are R0 and R1 pull-up
|
||||
resistors available, but for user, it's only need to set R1R0 as 00, 01,
|
||||
10 or 11. So It needs config "mediatek,pull-up-adv" or
|
||||
"mediatek,pull-down-adv" to support arguments for those special pins.
|
||||
Valid arguments are from 0 to 3.
|
||||
|
||||
mediatek,tdsel: An integer describing the steps for output level shifter
|
||||
duty cycle when asserted (high pulse width adjustment). Valid arguments
|
||||
are from 0 to 15.
|
||||
mediatek,rdsel: An integer describing the steps for input level shifter
|
||||
duty cycle when asserted (high pulse width adjustment). Valid arguments
|
||||
are from 0 to 63.
|
||||
|
||||
When config drive-strength, it can support some arguments, such as
|
||||
MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
|
||||
It can only support 2/4/6/8/10/12/14/16mA in mt8183.
|
||||
For I2C pins, there are existing generic driving setup and the specific
|
||||
driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving
|
||||
adjustment in generic driving setup. But in specific driving setup,
|
||||
they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
|
||||
driving setup for I2C pins, the existing generic driving setup will be
|
||||
disabled. For some special features, we need the I2C pins specific
|
||||
driving setup. The specific driving setup is controlled by E1E0EN.
|
||||
So we need add extra vendor driving preperty instead of
|
||||
the generic driving property.
|
||||
We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific
|
||||
driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1.
|
||||
It is used to enable or disable the specific driving setup.
|
||||
E1E0 is used to describe the detail strength specification of the I2C pin.
|
||||
When E1=0/E0=0, the strength is 0.125mA.
|
||||
When E1=0/E0=1, the strength is 0.25mA.
|
||||
When E1=1/E0=0, the strength is 0.5mA.
|
||||
When E1=1/E0=1, the strength is 1mA.
|
||||
So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7.
|
||||
|
||||
Examples:
|
||||
|
||||
#include "mt8183-pinfunc.h"
|
||||
|
||||
...
|
||||
{
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8183-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>,
|
||||
<0 0x11f20000 0 0x1000>,
|
||||
<0 0x11e80000 0 0x1000>,
|
||||
<0 0x11e70000 0 0x1000>,
|
||||
<0 0x11e90000 0 0x1000>,
|
||||
<0 0x11d30000 0 0x1000>,
|
||||
<0 0x11d20000 0 0x1000>,
|
||||
<0 0x11c50000 0 0x1000>,
|
||||
<0 0x11f30000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg1", "iocfg2",
|
||||
"iocfg3", "iocfg4", "iocfg5",
|
||||
"iocfg6", "iocfg7", "iocfg8",
|
||||
"eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 192>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
i2c0_pins_a: i2c0 {
|
||||
pins1 {
|
||||
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
|
||||
<PINMUX_GPIO49__FUNC_SDA5>;
|
||||
mediatek,pull-up-adv = <3>;
|
||||
mediatek,drive-strength-adv = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1 {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
|
||||
<PINMUX_GPIO51__FUNC_SDA3>;
|
||||
mediatek,pull-down-adv = <2>;
|
||||
mediatek,drive-strength-adv = <4>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
};
|
||||
@@ -57,6 +57,8 @@ Optional properties:
|
||||
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
|
||||
used to select GPIOs as interrupts).
|
||||
- hwlocks: reference to a phandle of a hardware spinlock provider node.
|
||||
- st,package: Indicates the SOC package used.
|
||||
More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
|
||||
|
||||
Example 1:
|
||||
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
|
||||
|
||||
Reference in New Issue
Block a user