@@ -49,6 +49,7 @@ struct msm_mmu;
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struct msm_rd_state;
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struct msm_perf_state;
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struct msm_gem_submit;
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struct msm_fence_cb;
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#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
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@@ -157,20 +158,6 @@ struct msm_format {
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uint32_t pixel_format;
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};
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/* callback from wq once fence has passed: */
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struct msm_fence_cb {
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struct work_struct work;
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uint32_t fence;
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void (*func)(struct msm_fence_cb *cb);
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};
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void __msm_fence_worker(struct work_struct *work);
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#define INIT_FENCE_CB(_cb, _func) do { \
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INIT_WORK(&(_cb)->work, __msm_fence_worker); \
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(_cb)->func = _func; \
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} while (0)
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int msm_atomic_check(struct drm_device *dev,
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struct drm_atomic_state *state);
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int msm_atomic_commit(struct drm_device *dev,
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@@ -178,12 +165,6 @@ int msm_atomic_commit(struct drm_device *dev,
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int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
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int msm_wait_fence(struct drm_device *dev, uint32_t fence,
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ktime_t *timeout, bool interruptible);
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int msm_queue_fence_cb(struct drm_device *dev,
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struct msm_fence_cb *cb, uint32_t fence);
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void msm_update_fence(struct drm_device *dev, uint32_t fence);
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int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
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struct drm_file *file);
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@@ -303,12 +284,6 @@ u32 msm_readl(const void __iomem *addr);
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#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
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{
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struct msm_drm_private *priv = dev->dev_private;
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return priv->completed_fence >= fence;
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}
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static inline int align_pitch(int width, int bpp)
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{
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int bytespp = (bpp + 7) / 8;
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