KVM: MMU: Expose the LA57 feature to VM.
This patch exposes 5 level page table feature to the VM. At the same time, the canonical virtual address checking is extended to support both 48-bits and 57-bits address width. Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@@ -122,7 +122,7 @@ module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
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(KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
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#define KVM_CR4_GUEST_OWNED_BITS \
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(X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
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| X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
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| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
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#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
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#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
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@@ -3374,7 +3374,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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(!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
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return 1;
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if (is_noncanonical_address(data & PAGE_MASK) ||
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if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
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(data & MSR_IA32_BNDCFGS_RSVD))
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return 1;
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vmcs_write64(GUEST_BNDCFGS, data);
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@@ -7143,7 +7143,7 @@ static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
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* non-canonical form. This is the only check on the memory
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* destination for long mode!
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*/
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exn = is_noncanonical_address(*ret);
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exn = is_noncanonical_address(*ret, vcpu);
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} else if (is_protmode(vcpu)) {
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/* Protected mode: apply checks for segment validity in the
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* following order:
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@@ -7948,7 +7948,7 @@ static int handle_invvpid(struct kvm_vcpu *vcpu)
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switch (type) {
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case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
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if (is_noncanonical_address(operand.gla)) {
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if (is_noncanonical_address(operand.gla, vcpu)) {
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nested_vmx_failValid(vcpu,
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VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
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return kvm_skip_emulated_instruction(vcpu);
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