[PATCH] PCI: msi abstractions and support for altix
Abstract portions of the MSI core for platforms that do not use standard APIC interrupt controllers. This is implemented through a new arch-specific msi setup routine, and a set of msi ops which can be set on a per platform basis. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Mark Maule
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Greg Kroah-Hartman
Greg Kroah-Hartman
parent
c34b4c7344
commit
fd58e55fcf
@@ -6,6 +6,68 @@
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#ifndef MSI_H
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#define MSI_H
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/*
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* MSI operation vector. Used by the msi core code (drivers/pci/msi.c)
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* to abstract platform-specific tasks relating to MSI address generation
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* and resource management.
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*/
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struct msi_ops {
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/**
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* setup - generate an MSI bus address and data for a given vector
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* @pdev: PCI device context (in)
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* @vector: vector allocated by the msi core (in)
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* @addr_hi: upper 32 bits of PCI bus MSI address (out)
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* @addr_lo: lower 32 bits of PCI bus MSI address (out)
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* @data: MSI data payload (out)
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*
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* Description: The setup op is used to generate a PCI bus addres and
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* data which the msi core will program into the card MSI capability
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* registers. The setup routine is responsible for picking an initial
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* cpu to target the MSI at. The setup routine is responsible for
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* examining pdev to determine the MSI capabilities of the card and
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* generating a suitable address/data. The setup routine is
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* responsible for allocating and tracking any system resources it
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* needs to route the MSI to the cpu it picks, and for associating
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* those resources with the passed in vector.
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*
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* Returns 0 if the MSI address/data was successfully setup.
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**/
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int (*setup) (struct pci_dev *pdev, unsigned int vector,
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u32 *addr_hi, u32 *addr_lo, u32 *data);
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/**
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* teardown - release resources allocated by setup
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* @vector: vector context for resources (in)
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*
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* Description: The teardown op is used to release any resources
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* that were allocated in the setup routine associated with the passed
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* in vector.
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**/
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void (*teardown) (unsigned int vector);
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/**
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* target - retarget an MSI at a different cpu
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* @vector: vector context for resources (in)
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* @cpu: new cpu to direct vector at (in)
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* @addr_hi: new value of PCI bus upper 32 bits (in/out)
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* @addr_lo: new value of PCI bus lower 32 bits (in/out)
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*
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* Description: The target op is used to redirect an MSI vector
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* at a different cpu. addr_hi/addr_lo coming in are the existing
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* values that the MSI core has programmed into the card. The
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* target code is responsible for freeing any resources (if any)
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* associated with the old address, and generating a new PCI bus
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* addr_hi/addr_lo that will redirect the vector at the indicated cpu.
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**/
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void (*target) (unsigned int vector, unsigned int cpu,
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u32 *addr_hi, u32 *addr_lo);
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};
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extern int msi_register(struct msi_ops *ops);
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#include <asm/msi.h>
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/*
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@@ -63,67 +125,6 @@ extern int pci_vector_resources(int last, int nr_released);
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#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
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#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
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/*
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* MSI Defined Data Structures
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*/
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#define MSI_ADDRESS_HEADER 0xfee
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#define MSI_ADDRESS_HEADER_SHIFT 12
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#define MSI_ADDRESS_HEADER_MASK 0xfff000
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#define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f
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#define MSI_TARGET_CPU_MASK 0xff
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#define MSI_DELIVERY_MODE 0
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#define MSI_LEVEL_MODE 1 /* Edge always assert */
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#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
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#define MSI_PHYSICAL_MODE 0
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#define MSI_LOGICAL_MODE 1
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#define MSI_REDIRECTION_HINT_MODE 0
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struct msg_data {
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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__u32 vector : 8;
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__u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
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__u32 reserved_1 : 3;
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__u32 level : 1; /* 0: deassert | 1: assert */
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__u32 trigger : 1; /* 0: edge | 1: level */
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__u32 reserved_2 : 16;
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#elif defined(__BIG_ENDIAN_BITFIELD)
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__u32 reserved_2 : 16;
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__u32 trigger : 1; /* 0: edge | 1: level */
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__u32 level : 1; /* 0: deassert | 1: assert */
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__u32 reserved_1 : 3;
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__u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
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__u32 vector : 8;
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#else
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#error "Bitfield endianness not defined! Check your byteorder.h"
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#endif
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} __attribute__ ((packed));
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struct msg_address {
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union {
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struct {
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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__u32 reserved_1 : 2;
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__u32 dest_mode : 1; /*0:physic | 1:logic */
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__u32 redirection_hint: 1; /*0: dedicated CPU
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1: lowest priority */
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__u32 reserved_2 : 4;
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__u32 dest_id : 24; /* Destination ID */
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#elif defined(__BIG_ENDIAN_BITFIELD)
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__u32 dest_id : 24; /* Destination ID */
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__u32 reserved_2 : 4;
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__u32 redirection_hint: 1; /*0: dedicated CPU
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1: lowest priority */
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__u32 dest_mode : 1; /*0:physic | 1:logic */
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__u32 reserved_1 : 2;
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#else
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#error "Bitfield endianness not defined! Check your byteorder.h"
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#endif
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}u;
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__u32 value;
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}lo_address;
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__u32 hi_address;
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} __attribute__ ((packed));
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struct msi_desc {
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struct {
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__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
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@@ -132,7 +133,7 @@ struct msi_desc {
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__u8 reserved: 1; /* reserved */
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__u8 entry_nr; /* specific enabled entry */
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__u8 default_vector; /* default pre-assigned vector */
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__u8 current_cpu; /* current destination cpu */
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__u8 unused; /* formerly unused destination cpu*/
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}msi_attrib;
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struct {
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@@ -142,6 +143,14 @@ struct msi_desc {
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void __iomem *mask_base;
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struct pci_dev *dev;
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#ifdef CONFIG_PM
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/* PM save area for MSIX address/data */
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u32 address_hi_save;
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u32 address_lo_save;
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u32 data_save;
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#endif
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};
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#endif /* MSI_H */
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