Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "We have two changes to the core framework this time around. The first being a large change that introduces runtime PM support to the clk framework. Now we properly call runtime PM operations on the device providing a clk when the clk is in use. This helps on SoCs where the clks provided by a device need something to be powered on before using the clks, like power domains or regulators. It also helps power those things down when clks aren't in use. The other core change is a devm API addition for clk providers so we can get rid of a bunch of clk driver remove functions that are just doing of_clk_del_provider(). Outside of the core, we have the usual addition of clk drivers and smattering of non-critical fixes to existing drivers. The biggest diff is support for Mediatek MT2712 and MT7622 SoCs, but those patches really just add a bunch of data. By the way, we're trying something new here where we build the tree up with topic branches. We plan to work this into our workflow so that we don't step on each other's toes, and so the fixes branch can be merged on an as-needed basis. Summary: Core: - runtime PM support for clk providers - devm API for of_clk_add_hw_provider() New Drivers: - Mediatek MT2712 and MT7622 - Renesas R-Car V3M SoC Updates: - runtime PM support for Samsung exynos5433/exynos4412 providers - removal of clkdev aliases on Samsung SoCs - convert clk-gpio to use gpio descriptors - various driver cleanups to match kernel coding style - Amlogic Video Processing Unit VPU and VAPB clks - sigma-delta modulation for Allwinner audio PLLs - Allwinner A83t Display clks - support for the second display unit clock on Renesas RZ/G1E - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR - new clock ids for Rockchip rk3188 and rk3368 SoCs - various 'const' markings on clk_ops structures - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: stm32h7: fix test of clock config clk: pxa: fix building on older compilers clk: sunxi-ng: a83t: Fix i2c buses bits clk: ti: dra7-atl-clock: fix child-node lookups clk: qcom: common: fix legacy board-clock registration clk: uniphier: fix DAPLL2 clock rate of Pro5 clk: uniphier: fix parent of miodmac clock data clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: kona-setup: Delete error messages for failed memory allocations ARC: clk: fix spelling mistake: "configurarion" -> "configuration" clk: cdce925: remove redundant check for non-null parent_name clk: versatile: Improve sizeof() usage clk: versatile: Delete error messages for failed memory allocations clk: ux500: Improve sizeof() usage clk: ux500: Delete error messages for failed memory allocations clk: spear: Delete error messages for failed memory allocations clk: ti: Delete error messages for failed memory allocations clk: mmp: Adjust checks for NULL pointers ...
This commit is contained in:
Linus Torvalds
@@ -7,7 +7,9 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-apmixedsys"
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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- "mediatek,mt7622-apmixedsys"
|
||||
- "mediatek,mt8135-apmixedsys"
|
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- "mediatek,mt8173-apmixedsys"
|
||||
- #clock-cells: Must be 1
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||||
|
||||
@@ -0,0 +1,22 @@
|
||||
MediaTek AUDSYS controller
|
||||
============================
|
||||
|
||||
The MediaTek AUDSYS controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
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- "mediatek,mt7622-audsys", "syscon"
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- #clock-cells: Must be 1
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|
||||
The AUDSYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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|
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Example:
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|
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audsys: audsys@11220000 {
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compatible = "mediatek,mt7622-audsys", "syscon";
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reg = <0 0x11220000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt2701-bdpsys", "syscon"
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- "mediatek,mt2712-bdpsys", "syscon"
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||||
- #clock-cells: Must be 1
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||||
|
||||
The bdpsys controller uses the common clk binding from
|
||||
|
||||
@@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be:
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||||
- "mediatek,mt2701-ethsys", "syscon"
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- "mediatek,mt7622-ethsys", "syscon"
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- #clock-cells: Must be 1
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|
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The ethsys controller uses the common clk binding from
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@@ -8,6 +8,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be:
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||||
- "mediatek,mt2701-hifsys", "syscon"
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- "mediatek,mt7622-hifsys", "syscon"
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- #clock-cells: Must be 1
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|
||||
The hifsys controller uses the common clk binding from
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|
||||
@@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- #clock-cells: Must be 1
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|
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@@ -8,7 +8,9 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
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- "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
|
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- #clock-cells: Must be 1
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|
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@@ -0,0 +1,22 @@
|
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Mediatek jpgdecsys controller
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============================
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The Mediatek jpgdecsys controller provides various clocks to the system.
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Required Properties:
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|
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- compatible: Should be:
|
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- "mediatek,mt2712-jpgdecsys", "syscon"
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- #clock-cells: Must be 1
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The jpgdecsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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jpgdecsys: syscon@19000000 {
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compatible = "mediatek,mt2712-jpgdecsys", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -0,0 +1,22 @@
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Mediatek mcucfg controller
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============================
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The Mediatek mcucfg controller provides various clocks to the system.
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Required Properties:
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|
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- compatible: Should be one of:
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- "mediatek,mt2712-mcucfg", "syscon"
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- #clock-cells: Must be 1
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|
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The mcucfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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||||
|
||||
Example:
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mcucfg: syscon@10220000 {
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compatible = "mediatek,mt2712-mcucfg", "syscon";
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reg = <0 0x10220000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -0,0 +1,22 @@
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Mediatek mfgcfg controller
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============================
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|
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The Mediatek mfgcfg controller provides various clocks to the system.
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Required Properties:
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||||
|
||||
- compatible: Should be one of:
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- "mediatek,mt2712-mfgcfg", "syscon"
|
||||
- #clock-cells: Must be 1
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||||
|
||||
The mfgcfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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|
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Example:
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mfgcfg: syscon@13000000 {
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compatible = "mediatek,mt2712-mfgcfg", "syscon";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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||||
};
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@@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt2712-mmsys", "syscon"
|
||||
- "mediatek,mt6797-mmsys", "syscon"
|
||||
- "mediatek,mt8173-mmsys", "syscon"
|
||||
- #clock-cells: Must be 1
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||||
|
||||
@@ -0,0 +1,22 @@
|
||||
MediaTek PCIESYS controller
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||||
============================
|
||||
|
||||
The MediaTek PCIESYS controller provides various clocks to the system.
|
||||
|
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Required Properties:
|
||||
|
||||
- compatible: Should be:
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||||
- "mediatek,mt7622-pciesys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The PCIESYS controller uses the common clk binding from
|
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Documentation/devicetree/bindings/clock/clock-bindings.txt
|
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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pciesys: pciesys@1a100800 {
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compatible = "mediatek,mt7622-pciesys", "syscon";
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reg = <0 0x1a100800 0 0x1000>;
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#clock-cells = <1>;
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||||
};
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@@ -8,6 +8,8 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
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- "mediatek,mt2701-pericfg", "syscon"
|
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- "mediatek,mt2712-pericfg", "syscon"
|
||||
- "mediatek,mt7622-pericfg", "syscon"
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||||
- "mediatek,mt8135-pericfg", "syscon"
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||||
- "mediatek,mt8173-pericfg", "syscon"
|
||||
- #clock-cells: Must be 1
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||||
|
||||
@@ -0,0 +1,22 @@
|
||||
MediaTek SGMIISYS controller
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||||
============================
|
||||
|
||||
The MediaTek SGMIISYS controller provides various clocks to the system.
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||||
|
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Required Properties:
|
||||
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||||
- compatible: Should be:
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||||
- "mediatek,mt7622-sgmiisys", "syscon"
|
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- #clock-cells: Must be 1
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||||
|
||||
The SGMIISYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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|
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Example:
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sgmiisys: sgmiisys@1b128000 {
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compatible = "mediatek,mt7622-sgmiisys", "syscon";
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reg = <0 0x1b128000 0 0x1000>;
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#clock-cells = <1>;
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||||
};
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@@ -0,0 +1,22 @@
|
||||
MediaTek SSUSBSYS controller
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||||
============================
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||||
|
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The MediaTek SSUSBSYS controller provides various clocks to the system.
|
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||||
Required Properties:
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||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt7622-ssusbsys", "syscon"
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||||
- #clock-cells: Must be 1
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||||
|
||||
The SSUSBSYS controller uses the common clk binding from
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||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
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||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7622-ssusbsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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||||
};
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@@ -7,7 +7,9 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt2712-topckgen", "syscon"
|
||||
- "mediatek,mt6797-topckgen"
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||||
- "mediatek,mt7622-topckgen"
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||||
- "mediatek,mt8135-topckgen"
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||||
- "mediatek,mt8173-topckgen"
|
||||
- #clock-cells: Must be 1
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|
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@@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt2712-vdecsys", "syscon"
|
||||
- "mediatek,mt6797-vdecsys", "syscon"
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||||
- "mediatek,mt8173-vdecsys", "syscon"
|
||||
- #clock-cells: Must be 1
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||||
|
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@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system.
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||||
Required Properties:
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||||
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- compatible: Should be one of:
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||||
- "mediatek,mt2712-vencsys", "syscon"
|
||||
- "mediatek,mt6797-vencsys", "syscon"
|
||||
- "mediatek,mt8173-vencsys", "syscon"
|
||||
- #clock-cells: Must be 1
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||||
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@@ -33,6 +33,12 @@ Required Properties:
|
||||
- clock-names: Aliases for the above clocks. They should be "pll_ref",
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"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
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||||
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Optional Properties:
|
||||
|
||||
- power-domains: a phandle to respective power domain node as described by
|
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generic PM domain bindings (see power/power_domain.txt for more
|
||||
information).
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
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||||
assigned an identifier and client nodes use this identifier to specify the
|
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clock which they consume. Some of the clocks are available only on a particular
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@@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock
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clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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};
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Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
|
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subsystem. Registers for those clocks are located in the ISP power domain.
|
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Because those registers are also located in a different memory region than
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the main clock controller, a separate clock controller has to be defined for
|
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handling them.
|
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|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,exynos4412-isp-clock".
|
||||
|
||||
- reg: physical base address of the ISP clock controller and length of memory
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||||
mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: list of the clock controller input clock identifiers,
|
||||
from common clock bindings, should point to CLK_ACLK200 and
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CLK_ACLK400_MCUISP clocks from the main clock controller.
|
||||
|
||||
- clock-names: list of the clock controller input clock names,
|
||||
as described in clock-bindings.txt, should be "aclk200" and
|
||||
"aclk400_mcuisp".
|
||||
|
||||
- power-domains: a phandle to ISP power domain node as described by
|
||||
generic PM domain bindings.
|
||||
|
||||
Example 3: The clock controllers bindings for Exynos4412 SoCs.
|
||||
|
||||
clock: clock-controller@10030000 {
|
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compatible = "samsung,exynos4412-clock";
|
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reg = <0x10030000 0x18000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
isp_clock: clock-controller@10048000 {
|
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compatible = "samsung,exynos4412-isp-clock";
|
||||
reg = <0x10048000 0x1000>;
|
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#clock-cells = <1>;
|
||||
power-domains = <&pd_isp>;
|
||||
clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
|
||||
clock-names = "aclk200", "aclk400_mcuisp";
|
||||
};
|
||||
|
||||
@@ -168,6 +168,11 @@ Required Properties:
|
||||
- aclk_cam1_400
|
||||
- aclk_cam1_552
|
||||
|
||||
Optional properties:
|
||||
- power-domains: a phandle to respective power domain node as described by
|
||||
generic PM domain bindings (see power/power_domain.txt for more
|
||||
information).
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
@@ -270,6 +275,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_G2D_266>,
|
||||
<&cmu_top CLK_ACLK_G2D_400>;
|
||||
power-domains = <&pd_g2d>;
|
||||
};
|
||||
|
||||
cmu_disp: clock-controller@13b90000 {
|
||||
@@ -295,6 +301,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
|
||||
<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
|
||||
<&cmu_mif CLK_ACLK_DISP_333>;
|
||||
power-domains = <&pd_disp>;
|
||||
};
|
||||
|
||||
cmu_aud: clock-controller@114c0000 {
|
||||
@@ -304,6 +311,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
|
||||
clock-names = "oscclk", "fout_aud_pll";
|
||||
clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
|
||||
power-domains = <&pd_aud>;
|
||||
};
|
||||
|
||||
cmu_bus0: clock-controller@13600000 {
|
||||
@@ -340,6 +348,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
|
||||
clock-names = "oscclk", "aclk_g3d_400";
|
||||
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
|
||||
power-domains = <&pd_g3d>;
|
||||
};
|
||||
|
||||
cmu_gscl: clock-controller@13cf0000 {
|
||||
@@ -353,6 +362,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_GSCL_111>,
|
||||
<&cmu_top CLK_ACLK_GSCL_333>;
|
||||
power-domains = <&pd_gscl>;
|
||||
};
|
||||
|
||||
cmu_apollo: clock-controller@11900000 {
|
||||
@@ -384,6 +394,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_SCLK_JPEG_MSCL>,
|
||||
<&cmu_top CLK_ACLK_MSCL_400>;
|
||||
power-domains = <&pd_mscl>;
|
||||
};
|
||||
|
||||
cmu_mfc: clock-controller@15280000 {
|
||||
@@ -393,6 +404,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
|
||||
clock-names = "oscclk", "aclk_mfc_400";
|
||||
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
|
||||
power-domains = <&pd_mfc>;
|
||||
};
|
||||
|
||||
cmu_hevc: clock-controller@14f80000 {
|
||||
@@ -402,6 +414,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
|
||||
clock-names = "oscclk", "aclk_hevc_400";
|
||||
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
|
||||
power-domains = <&pd_hevc>;
|
||||
};
|
||||
|
||||
cmu_isp: clock-controller@146d0000 {
|
||||
@@ -415,6 +428,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
clocks = <&xxti>,
|
||||
<&cmu_top CLK_ACLK_ISP_DIS_400>,
|
||||
<&cmu_top CLK_ACLK_ISP_400>;
|
||||
power-domains = <&pd_isp>;
|
||||
};
|
||||
|
||||
cmu_cam0: clock-controller@120d0000 {
|
||||
@@ -430,6 +444,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
<&cmu_top CLK_ACLK_CAM0_333>,
|
||||
<&cmu_top CLK_ACLK_CAM0_400>,
|
||||
<&cmu_top CLK_ACLK_CAM0_552>;
|
||||
power-domains = <&pd_cam0>;
|
||||
};
|
||||
|
||||
cmu_cam1: clock-controller@145d0000 {
|
||||
@@ -451,6 +466,7 @@ Example 2: Examples of clock controller nodes are listed below.
|
||||
<&cmu_top CLK_ACLK_CAM1_333>,
|
||||
<&cmu_top CLK_ACLK_CAM1_400>,
|
||||
<&cmu_top CLK_ACLK_CAM1_552>;
|
||||
power-domains = <&pd_cam1>;
|
||||
};
|
||||
|
||||
Example 3: UART controller node that consumes the clock generated by the clock
|
||||
|
||||
@@ -10,12 +10,23 @@ Required properties :
|
||||
- compatible : shall contain only one of the following. The generic
|
||||
compatible "qcom,rpmcc" should be also included.
|
||||
|
||||
"qcom,rpmcc-msm8660", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h>
|
||||
and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock
|
||||
is an "active" clock, which means that the consumer only care that the
|
||||
clock is available when the apps CPU subsystem is active, i.e. not
|
||||
suspended or in deep idle. If it is important that the clock keeps running
|
||||
during system suspend, you need to specify the non-active clock, the one
|
||||
not containing *_A_* in the enumerator name.
|
||||
|
||||
Example:
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
@@ -22,6 +22,7 @@ Required Properties:
|
||||
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
|
||||
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG/MSSR
|
||||
@@ -31,8 +32,8 @@ Required Properties:
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
|
||||
r8a7795, r8a7796, r8a77995)
|
||||
- "extalr" (r8a7795, r8a7796)
|
||||
r8a7795, r8a7796, r8a77970, r8a77995)
|
||||
- "extalr" (r8a7795, r8a7796, r8a77970)
|
||||
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
|
||||
|
||||
- #clock-cells: Must be 2
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
* Renesas RZ Clock Pulse Generator (CPG)
|
||||
* Renesas RZ/A1 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
|
||||
The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
|
||||
CPU and GPU clocks, and several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
@@ -237,6 +237,7 @@ CLOCK
|
||||
devm_clk_get()
|
||||
devm_clk_put()
|
||||
devm_clk_hw_register()
|
||||
devm_of_clk_add_hw_provider()
|
||||
|
||||
DMA
|
||||
dmam_alloc_coherent()
|
||||
|
||||
Reference in New Issue
Block a user