xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

MIPS: Cleanup indentation and whitespace

Browse Source 
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5536/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Tony Wu
2013-06-21 10:10:46 +00:00
committed by Ralf Baechle
parent 4df715aaf5
commit fc192e50f8
6 changed files with 22 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
arch/mips/include/asm/cpu-features.h
View File

@@ -97,13 +97,13 @@
#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif #endif
#ifndef cpu_has_mdmx #ifndef cpu_has_mdmx
#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
#endif #endif
#ifndef cpu_has_mips3d #ifndef cpu_has_mips3d
#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
#endif #endif
#ifndef cpu_has_smartmips #ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif #endif
#ifndef cpu_has_rixi #ifndef cpu_has_rixi
#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
@@ -125,7 +125,7 @@
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif #endif
#ifndef cpu_has_pindexed_dcache #ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif #endif
#ifndef cpu_has_local_ebase #ifndef cpu_has_local_ebase
#define cpu_has_local_ebase 1 #define cpu_has_local_ebase 1
@@ -162,18 +162,18 @@
#ifndef cpu_has_mips_5 #ifndef cpu_has_mips_5
# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
#endif #endif
# ifndef cpu_has_mips32r1 #ifndef cpu_has_mips32r1
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
# endif #endif
# ifndef cpu_has_mips32r2 #ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
# endif #endif
# ifndef cpu_has_mips64r1 #ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
# endif #endif
# ifndef cpu_has_mips64r2 #ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
# endif #endif
/* /*
* Shortcuts ... * Shortcuts ...
@@ -195,9 +195,9 @@
* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/ */
# ifndef cpu_has_clo_clz #ifndef cpu_has_clo_clz
# define cpu_has_clo_clz cpu_has_mips_r #define cpu_has_clo_clz cpu_has_mips_r
# endif #endif
#ifndef cpu_has_dsp #ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
@@ -223,7 +223,7 @@
# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif # endif
# ifndef cpu_has_64bit_zero_reg # ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif # endif
# ifndef cpu_has_64bit_gp_regs # ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 0 # define cpu_has_64bit_gp_regs 0

4
arch/mips/include/asm/mach-generic/kernel-entry-init.h
View File

@@ -12,8 +12,8 @@
/* Intentionally empty macro, used in head.S. Override in /* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary. * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/ */
.macro kernel_entry_setup .macro kernel_entry_setup
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can savely execute C code.

4
arch/mips/include/asm/processor.h
View File

@@ -244,8 +244,8 @@ struct thread_struct {
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
unsigned long error_code; unsigned long error_code;
#ifdef CONFIG_CPU_CAVIUM_OCTEON #ifdef CONFIG_CPU_CAVIUM_OCTEON
struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
#endif #endif
#ifdef CONFIG_CPU_XLP #ifdef CONFIG_CPU_XLP
struct nlm_cop2_state cp2; struct nlm_cop2_state cp2;

1
arch/mips/kernel/branch.c
View File

@@ -467,5 +467,4 @@ unaligned:
printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
force_sig(SIGBUS, current); force_sig(SIGBUS, current);
return -EFAULT; return -EFAULT;
} }

1
arch/mips/kernel/unaligned.c
View File

@@ -1549,6 +1549,7 @@ sigill:
("Unhandled kernel unaligned access or invalid instruction", regs); ("Unhandled kernel unaligned access or invalid instruction", regs);
force_sig(SIGILL, current); force_sig(SIGILL, current);
} }
asmlinkage void do_ade(struct pt_regs *regs) asmlinkage void do_ade(struct pt_regs *regs)
{ {
enum ctx_state prev_state; enum ctx_state prev_state;

2
arch/mips/mm/page.c
View File

@@ -232,7 +232,7 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
} }
} }
} }
extern u32 __clear_page_start; extern u32 __clear_page_start;