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MIPS: Cleanup indentation and whitespace

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Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5536/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Tony Wu
2013-06-21 10:10:46 +00:00
committed by Ralf Baechle
parent 4df715aaf5
commit fc192e50f8
6 changed files with 22 additions and 22 deletions
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22
arch/mips/include/asm/cpu-features.h
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@@ -162,18 +162,18 @@
#ifndef cpu_has_mips_5 #ifndef cpu_has_mips_5
# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
#endif #endif
# ifndef cpu_has_mips32r1 #ifndef cpu_has_mips32r1
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
# endif #endif
# ifndef cpu_has_mips32r2 #ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
# endif #endif
# ifndef cpu_has_mips64r1 #ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
# endif #endif
# ifndef cpu_has_mips64r2 #ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
# endif #endif
/* /*
* Shortcuts ... * Shortcuts ...
@@ -195,9 +195,9 @@
* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/ */
# ifndef cpu_has_clo_clz #ifndef cpu_has_clo_clz
# define cpu_has_clo_clz cpu_has_mips_r #define cpu_has_clo_clz cpu_has_mips_r
# endif #endif
#ifndef cpu_has_dsp #ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)

4
arch/mips/include/asm/mach-generic/kernel-entry-init.h
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@@ -12,8 +12,8 @@
/* Intentionally empty macro, used in head.S. Override in /* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary. * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/ */
.macro kernel_entry_setup .macro kernel_entry_setup
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can savely execute C code.

1
arch/mips/kernel/branch.c
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@@ -467,5 +467,4 @@ unaligned:
printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
force_sig(SIGBUS, current); force_sig(SIGBUS, current);
return -EFAULT; return -EFAULT;
} }

1
arch/mips/kernel/unaligned.c
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@@ -1549,6 +1549,7 @@ sigill:
("Unhandled kernel unaligned access or invalid instruction", regs); ("Unhandled kernel unaligned access or invalid instruction", regs);
force_sig(SIGILL, current); force_sig(SIGILL, current);
} }
asmlinkage void do_ade(struct pt_regs *regs) asmlinkage void do_ade(struct pt_regs *regs)
{ {
enum ctx_state prev_state; enum ctx_state prev_state;