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net/mlx5e: Add HW cacheline start padding

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Enable HW cacheline start padding and align RX WQE size to cacheline
while considering HW start padding. Also, fix dma_unmap call to use
the correct SKB data buffer size.

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Saeed Mahameed
2015-06-11 14:47:28 +03:00
committed by David S. Miller
parent facc9699f0
commit fc11fbf9a7
3 changed files with 13 additions and 6 deletions
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4
include/linux/mlx5/device.h
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@@ -131,6 +131,10 @@ enum {
MLX5_INLINE_SEG = 0x80000000,
};
enum {
MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
};
enum {
MLX5_MIN_PKEY_TABLE_SIZE = 128,
MLX5_MAX_LOG_PKEY_TABLE = 5,