Merge tag 'soc-fsl-next-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers
NXP/FSL SoC driver updates for v5.8 DPAA2 DPIO driver - Prefer the CPU affined DPIO QUICC Engine drivers - Replace one-element array and use struct_size() helper Cleanups in various drivers * tag 'soc-fsl-next-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: soc: fsl: dpio: Remove unused inline function qbman_write_eqcr_am_rt_register soc: fsl: qe: clean up an indentation issue soc: fsl: dpio: Prefer the CPU affine DPIO soc: fsl: qbman: Remove unused inline function qm_eqcr_get_ci_stashing soc: fsl: qe: Replace one-element array and use struct_size() helper treewide: Replace zero-length array with flexible-array Link: https://lore.kernel.org/r/20200527215740.9279-1-leoyang.li@nxp.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@@ -58,7 +58,7 @@ static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
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* If cpu == -1, choose the current cpu, with no guarantees about
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* potentially being migrated away.
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*/
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if (unlikely(cpu < 0))
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if (cpu < 0)
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cpu = smp_processor_id();
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/* If a specific cpu was requested, pick it up immediately */
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@@ -70,6 +70,10 @@ static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
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if (d)
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return d;
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d = service_select_by_cpu(d, -1);
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if (d)
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return d;
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spin_lock(&dpio_list_lock);
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d = list_entry(dpio_list.next, struct dpaa2_io, node);
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list_del(&d->node);
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@@ -572,18 +572,6 @@ void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
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#define EQAR_VB(eqar) ((eqar) & 0x80)
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#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
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static inline void qbman_write_eqcr_am_rt_register(struct qbman_swp *p,
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u8 idx)
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{
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if (idx < 16)
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qbman_write_register(p, QBMAN_CINH_SWP_EQCR_AM_RT + idx * 4,
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QMAN_RT_MODE);
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else
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qbman_write_register(p, QBMAN_CINH_SWP_EQCR_AM_RT2 +
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(idx - 16) * 4,
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QMAN_RT_MODE);
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}
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#define QB_RT_BIT ((u32)0x100)
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/**
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* qbman_swp_enqueue_direct() - Issue an enqueue command
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@@ -449,11 +449,6 @@ static inline int qm_eqcr_init(struct qm_portal *portal,
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return 0;
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}
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static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
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{
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return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
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}
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static inline void qm_eqcr_finish(struct qm_portal *portal)
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{
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struct qm_eqcr *eqcr = &portal->eqcr;
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@@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
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unsigned int i;
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unsigned int j;
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u32 crc;
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size_t calc_size = sizeof(struct qe_firmware);
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size_t calc_size;
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size_t length;
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const struct qe_header *hdr;
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@@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
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}
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/* Validate the length and check if there's a CRC */
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calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
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calc_size = struct_size(firmware, microcode, firmware->count);
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for (i = 0; i < firmware->count; i++)
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/*
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@@ -27,7 +27,7 @@
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*/
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struct bcom_bd {
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u32 status;
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u32 data[0]; /* variable payload size */
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u32 data[]; /* variable payload size */
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};
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/* ======================================================================== */
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@@ -307,7 +307,7 @@ struct qe_firmware {
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u8 revision; /* The microcode version revision */
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u8 padding; /* Reserved, for alignment */
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u8 reserved[4]; /* Reserved, for future expansion */
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} __attribute__ ((packed)) microcode[1];
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} __packed microcode[];
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/* All microcode binaries should be located here */
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/* CRC32 should be located here, after the microcode binaries */
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} __attribute__ ((packed));
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