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net: ipa: simplify ipa_endpoint_program()

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Have functions that write endpoint configuration registers return
immediately if they are not valid for the direction of transfer for
the endpoint.  This allows most of the calls in ipa_endpoint_program()
to be made unconditionally.  Reorder the register writes to match
the order of their definition (based on offset).

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Elder
2020-07-02 06:25:37 -05:00
committed by David S. Miller
parent b07f283ef3
commit fb57c3ea98
1 changed files with 20 additions and 11 deletions
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31
drivers/net/ipa/ipa_endpoint.c
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@@ -588,6 +588,9 @@ static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
u32 val = 0; u32 val = 0;
u32 offset; u32 offset;
if (endpoint->toward_ipa)
return; /* Register not valid for TX endpoints */
offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id); offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id);
/* Note that HDR_ENDIANNESS indicates big endian header fields */ /* Note that HDR_ENDIANNESS indicates big endian header fields */
@@ -602,6 +605,9 @@ static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id); u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id);
u32 val; u32 val;
if (!endpoint->toward_ipa)
return; /* Register not valid for RX endpoints */
if (endpoint->data->dma_mode) { if (endpoint->data->dma_mode) {
enum ipa_endpoint_name name = endpoint->data->dma_endpoint; enum ipa_endpoint_name name = endpoint->data->dma_endpoint;
u32 dma_endpoint_id; u32 dma_endpoint_id;
@@ -760,6 +766,9 @@ static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id); u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id);
u32 val = 0; u32 val = 0;
if (!endpoint->toward_ipa)
return; /* Register not valid for RX endpoints */
/* DEAGGR_HDR_LEN is 0 */ /* DEAGGR_HDR_LEN is 0 */
/* PACKET_OFFSET_VALID is 0 */ /* PACKET_OFFSET_VALID is 0 */
/* PACKET_OFFSET_LOCATION is ignored (not valid) */ /* PACKET_OFFSET_LOCATION is ignored (not valid) */
@@ -774,6 +783,9 @@ static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
u32 seq_type = endpoint->seq_type; u32 seq_type = endpoint->seq_type;
u32 val = 0; u32 val = 0;
if (!endpoint->toward_ipa)
return; /* Register not valid for RX endpoints */
/* Sequencer type is made up of four nibbles */ /* Sequencer type is made up of four nibbles */
val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK); val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK);
val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK); val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK);
@@ -1330,21 +1342,18 @@ static void ipa_endpoint_reset(struct ipa_endpoint *endpoint)
static void ipa_endpoint_program(struct ipa_endpoint *endpoint) static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
{ {
if (endpoint->toward_ipa) { if (endpoint->toward_ipa)
ipa_endpoint_program_delay(endpoint, false); ipa_endpoint_program_delay(endpoint, false);
ipa_endpoint_init_hdr_ext(endpoint); else
ipa_endpoint_init_aggr(endpoint);
ipa_endpoint_init_deaggr(endpoint);
ipa_endpoint_init_seq(endpoint);
ipa_endpoint_init_mode(endpoint);
} else {
(void)ipa_endpoint_program_suspend(endpoint, false); (void)ipa_endpoint_program_suspend(endpoint, false);
ipa_endpoint_init_hdr_ext(endpoint);
ipa_endpoint_init_aggr(endpoint);
ipa_endpoint_init_hdr_metadata_mask(endpoint);
}
ipa_endpoint_init_cfg(endpoint); ipa_endpoint_init_cfg(endpoint);
ipa_endpoint_init_hdr(endpoint); ipa_endpoint_init_hdr(endpoint);
ipa_endpoint_init_hdr_ext(endpoint);
ipa_endpoint_init_hdr_metadata_mask(endpoint);
ipa_endpoint_init_mode(endpoint);
ipa_endpoint_init_aggr(endpoint);
ipa_endpoint_init_deaggr(endpoint);
ipa_endpoint_init_seq(endpoint);
ipa_endpoint_status(endpoint); ipa_endpoint_status(endpoint);
} }