locking: Convert raw_rwlock to arch_rwlock
Not strictly necessary for -rt as -rt does not have non sleeping rwlocks, but it's odd to not have a consistent naming convention. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra <peterz@infradead.org> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: linux-arch@vger.kernel.org
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@@ -65,7 +65,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
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* Sort of like atomic_t's on Sparc, but even more clever.
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*
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* ------------------------------------
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* | 24-bit counter | wlock | raw_rwlock_t
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* | 24-bit counter | wlock | arch_rwlock_t
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* ------------------------------------
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* 31 8 7 0
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*
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@@ -76,9 +76,9 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
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*
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* Unfortunately this scheme limits us to ~16,000,000 cpus.
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*/
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static inline void arch_read_lock(raw_rwlock_t *rw)
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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register arch_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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@@ -96,9 +96,9 @@ do { unsigned long flags; \
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local_irq_restore(flags); \
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} while(0)
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static inline void arch_read_unlock(raw_rwlock_t *rw)
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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register arch_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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@@ -116,9 +116,9 @@ do { unsigned long flags; \
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local_irq_restore(flags); \
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} while(0)
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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static inline void __raw_write_lock(arch_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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register arch_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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@@ -130,7 +130,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
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*(volatile __u32 *)&lp->lock = ~0U;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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static inline int __raw_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int val;
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@@ -150,9 +150,9 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
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return (val == 0);
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}
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static inline int arch_read_trylock(raw_rwlock_t *rw)
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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register arch_rwlock_t *lp asm("g1");
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register int res asm("o0");
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lp = rw;
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__asm__ __volatile__(
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@@ -92,7 +92,7 @@ static inline void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long fla
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/* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
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static void inline arch_read_lock(raw_rwlock_t *lock)
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static void inline arch_read_lock(arch_rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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@@ -115,7 +115,7 @@ static void inline arch_read_lock(raw_rwlock_t *lock)
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: "memory");
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}
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static int inline arch_read_trylock(raw_rwlock_t *lock)
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static int inline arch_read_trylock(arch_rwlock_t *lock)
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{
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int tmp1, tmp2;
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@@ -136,7 +136,7 @@ static int inline arch_read_trylock(raw_rwlock_t *lock)
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return tmp1;
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}
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static void inline arch_read_unlock(raw_rwlock_t *lock)
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static void inline arch_read_unlock(arch_rwlock_t *lock)
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{
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unsigned long tmp1, tmp2;
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@@ -152,7 +152,7 @@ static void inline arch_read_unlock(raw_rwlock_t *lock)
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: "memory");
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}
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static void inline arch_write_lock(raw_rwlock_t *lock)
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static void inline arch_write_lock(arch_rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2;
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@@ -177,7 +177,7 @@ static void inline arch_write_lock(raw_rwlock_t *lock)
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: "memory");
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}
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static void inline arch_write_unlock(raw_rwlock_t *lock)
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static void inline arch_write_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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" stw %%g0, [%0]"
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@@ -186,7 +186,7 @@ static void inline arch_write_unlock(raw_rwlock_t *lock)
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: "memory");
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}
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static int inline arch_write_trylock(raw_rwlock_t *lock)
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static int inline arch_write_trylock(arch_rwlock_t *lock)
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{
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unsigned long mask, tmp1, tmp2, result;
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@@ -13,8 +13,8 @@ typedef struct {
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typedef struct {
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volatile unsigned int lock;
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} raw_rwlock_t;
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} arch_rwlock_t;
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#define __RAW_RW_LOCK_UNLOCKED { 0 }
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#define __ARCH_RW_LOCK_UNLOCKED { 0 }
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#endif
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