drm/msm: resync generated headers
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
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- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
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- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
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- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@@ -212,6 +214,20 @@ static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state
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#define REG_HDMI_HDCP_RESET 0x00000130
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#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
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#define REG_HDMI_VENSPEC_INFO0 0x0000016c
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#define REG_HDMI_VENSPEC_INFO1 0x00000170
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#define REG_HDMI_VENSPEC_INFO2 0x00000174
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#define REG_HDMI_VENSPEC_INFO3 0x00000178
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#define REG_HDMI_VENSPEC_INFO4 0x0000017c
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#define REG_HDMI_VENSPEC_INFO5 0x00000180
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#define REG_HDMI_VENSPEC_INFO6 0x00000184
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#define REG_HDMI_AUDIO_CFG 0x000001d0
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#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
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#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
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@@ -235,6 +251,9 @@ static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
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return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
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}
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#define REG_HDMI_DDC_ARBITRATION 0x00000210
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#define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
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#define REG_HDMI_DDC_INT_CTRL 0x00000214
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#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
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#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
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@@ -340,6 +359,20 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
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return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
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}
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#define REG_HDMI_CEC_STATUS 0x00000298
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#define REG_HDMI_CEC_INT 0x0000029c
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#define REG_HDMI_CEC_ADDR 0x000002a0
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#define REG_HDMI_CEC_TIME 0x000002a4
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#define REG_HDMI_CEC_REFTIMER 0x000002a8
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#define REG_HDMI_CEC_RD_DATA 0x000002ac
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#define REG_HDMI_CEC_RD_FILTER 0x000002b0
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#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
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#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
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#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
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@@ -410,17 +443,33 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
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#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
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#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
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#define REG_HDMI_AUD_INT 0x000002cc
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#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
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#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
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#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
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#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
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#define REG_HDMI_PHY_CTRL 0x000002d4
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#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
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#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
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#define HDMI_PHY_CTRL_SW_RESET 0x00000004
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#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
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#define REG_HDMI_AUD_INT 0x000002cc
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#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
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#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
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#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
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#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
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#define REG_HDMI_CEC_WR_RANGE 0x000002dc
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#define REG_HDMI_CEC_RD_RANGE 0x000002e0
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#define REG_HDMI_VERSION 0x000002e4
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#define REG_HDMI_CEC_COMPL_CTL 0x00000360
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#define REG_HDMI_CEC_RD_START_RANGE 0x00000364
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#define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
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#define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
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#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
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#define REG_HDMI_8x60_PHY_REG0 0x00000300
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#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
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@@ -504,5 +553,23 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
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#define REG_HDMI_8960_PHY_REG12 0x00000430
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#define REG_HDMI_8x74_ANA_CFG0 0x00000000
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#define REG_HDMI_8x74_ANA_CFG1 0x00000004
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#define REG_HDMI_8x74_PD_CTRL0 0x00000010
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#define REG_HDMI_8x74_PD_CTRL1 0x00000014
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#define REG_HDMI_8x74_BIST_CFG0 0x00000034
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#define REG_HDMI_8x74_BIST_PATN0 0x0000003c
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#define REG_HDMI_8x74_BIST_PATN1 0x00000040
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#define REG_HDMI_8x74_BIST_PATN2 0x00000044
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#define REG_HDMI_8x74_BIST_PATN3 0x00000048
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#endif /* HDMI_XML */
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