RISC-V: Atomic and Locking Code
This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
This commit is contained in:
Palmer Dabbelt
375
arch/riscv/include/asm/atomic.h
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375
arch/riscv/include/asm/atomic.h
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/*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_RISCV_ATOMIC_H
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#define _ASM_RISCV_ATOMIC_H
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#ifdef CONFIG_GENERIC_ATOMIC64
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# include <asm-generic/atomic64.h>
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#else
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# if (__riscv_xlen < 64)
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# error "64-bit atomics require XLEN to be at least 64"
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# endif
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#endif
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define ATOMIC_INIT(i) { (i) }
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static __always_inline int atomic_read(const atomic_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void atomic_set(atomic_t *v, int i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC64_INIT(i) { (i) }
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static __always_inline long atomic64_read(const atomic64_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void atomic64_set(atomic64_t *v, long i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#endif
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/*
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* First, the atomic ops that have no ordering constraints and therefor don't
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* have the AQ or RL bits set. These don't return anything, so there's only
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* one version to worry about.
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*/
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#define ATOMIC_OP(op, asm_op, c_op, I, asm_type, c_type, prefix) \
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static __always_inline void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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__asm__ __volatile__ ( \
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"amo" #asm_op "." #asm_type " zero, %1, %0" \
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: "+A" (v->counter) \
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: "r" (I) \
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: "memory"); \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_OP (op, asm_op, c_op, I, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_OP (op, asm_op, c_op, I, w, int, ) \
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ATOMIC_OP (op, asm_op, c_op, I, d, long, 64)
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#endif
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ATOMIC_OPS(add, add, +, i)
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ATOMIC_OPS(sub, add, +, -i)
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ATOMIC_OPS(and, and, &, i)
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ATOMIC_OPS( or, or, |, i)
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ATOMIC_OPS(xor, xor, ^, i)
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#undef ATOMIC_OP
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#undef ATOMIC_OPS
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/*
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* Atomic ops that have ordered, relaxed, acquire, and relese variants.
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* There's two flavors of these: the arithmatic ops have both fetch and return
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* versions, while the logical ops only have fetch versions.
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*/
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#define ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, asm_type, c_type, prefix) \
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static __always_inline c_type atomic##prefix##_fetch_##op##c_or(c_type i, atomic##prefix##_t *v) \
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{ \
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register c_type ret; \
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__asm__ __volatile__ ( \
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"amo" #asm_op "." #asm_type #asm_or " %1, %2, %0" \
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: "+A" (v->counter), "=r" (ret) \
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: "r" (I) \
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: "memory"); \
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return ret; \
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}
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#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, asm_type, c_type, prefix) \
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static __always_inline c_type atomic##prefix##_##op##_return##c_or(c_type i, atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##op##c_or(i, v) c_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I, asm_or, c_or) \
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ATOMIC_FETCH_OP (op, asm_op, c_op, I, asm_or, c_or, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I, asm_or, c_or) \
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ATOMIC_FETCH_OP (op, asm_op, c_op, I, asm_or, c_or, w, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, w, int, ) \
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ATOMIC_FETCH_OP (op, asm_op, c_op, I, asm_or, c_or, d, long, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_or, c_or, d, long, 64)
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#endif
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ATOMIC_OPS(add, add, +, i, , _relaxed)
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ATOMIC_OPS(add, add, +, i, .aq , _acquire)
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ATOMIC_OPS(add, add, +, i, .rl , _release)
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ATOMIC_OPS(add, add, +, i, .aqrl, )
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ATOMIC_OPS(sub, add, +, -i, , _relaxed)
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ATOMIC_OPS(sub, add, +, -i, .aq , _acquire)
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ATOMIC_OPS(sub, add, +, -i, .rl , _release)
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ATOMIC_OPS(sub, add, +, -i, .aqrl, )
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#undef ATOMIC_OPS
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I, asm_or, c_or) \
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ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, w, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I, asm_or, c_or) \
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ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, w, int, ) \
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ATOMIC_FETCH_OP(op, asm_op, c_op, I, asm_or, c_or, d, long, 64)
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#endif
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ATOMIC_OPS(and, and, &, i, , _relaxed)
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ATOMIC_OPS(and, and, &, i, .aq , _acquire)
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ATOMIC_OPS(and, and, &, i, .rl , _release)
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ATOMIC_OPS(and, and, &, i, .aqrl, )
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ATOMIC_OPS( or, or, |, i, , _relaxed)
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ATOMIC_OPS( or, or, |, i, .aq , _acquire)
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ATOMIC_OPS( or, or, |, i, .rl , _release)
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ATOMIC_OPS( or, or, |, i, .aqrl, )
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ATOMIC_OPS(xor, xor, ^, i, , _relaxed)
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ATOMIC_OPS(xor, xor, ^, i, .aq , _acquire)
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ATOMIC_OPS(xor, xor, ^, i, .rl , _release)
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ATOMIC_OPS(xor, xor, ^, i, .aqrl, )
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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/*
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* The extra atomic operations that are constructed from one of the core
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* AMO-based operations above (aside from sub, which is easier to fit above).
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* These are required to perform a barrier, but they're OK this way because
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* atomic_*_return is also required to perform a barrier.
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*/
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#define ATOMIC_OP(op, func_op, comp_op, I, c_type, prefix) \
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static __always_inline bool atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_##func_op##_return(i, v) comp_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, func_op, comp_op, I) \
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ATOMIC_OP (op, func_op, comp_op, I, int, )
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#else
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#define ATOMIC_OPS(op, func_op, comp_op, I) \
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ATOMIC_OP (op, func_op, comp_op, I, int, ) \
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ATOMIC_OP (op, func_op, comp_op, I, long, 64)
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#endif
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ATOMIC_OPS(add_and_test, add, ==, 0)
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ATOMIC_OPS(sub_and_test, sub, ==, 0)
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ATOMIC_OPS(add_negative, add, <, 0)
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#undef ATOMIC_OP
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#undef ATOMIC_OPS
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#define ATOMIC_OP(op, func_op, c_op, I, c_type, prefix) \
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static __always_inline void atomic##prefix##_##op(atomic##prefix##_t *v) \
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{ \
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atomic##prefix##_##func_op(I, v); \
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}
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#define ATOMIC_FETCH_OP(op, func_op, c_op, I, c_type, prefix) \
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static __always_inline c_type atomic##prefix##_fetch_##op(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##func_op(I, v); \
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}
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#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, c_type, prefix) \
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static __always_inline c_type atomic##prefix##_##op##_return(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_fetch_##op(v) c_op I; \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_OP (op, asm_op, c_op, I, int, ) \
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ATOMIC_FETCH_OP (op, asm_op, c_op, I, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, int, )
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#else
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#define ATOMIC_OPS(op, asm_op, c_op, I) \
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ATOMIC_OP (op, asm_op, c_op, I, int, ) \
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ATOMIC_FETCH_OP (op, asm_op, c_op, I, int, ) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, int, ) \
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ATOMIC_OP (op, asm_op, c_op, I, long, 64) \
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ATOMIC_FETCH_OP (op, asm_op, c_op, I, long, 64) \
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ATOMIC_OP_RETURN(op, asm_op, c_op, I, long, 64)
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#endif
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ATOMIC_OPS(inc, add, +, 1)
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ATOMIC_OPS(dec, add, +, -1)
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#undef ATOMIC_OPS
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#undef ATOMIC_OP
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#define ATOMIC_OP(op, func_op, comp_op, I, prefix) \
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static __always_inline bool atomic##prefix##_##op(atomic##prefix##_t *v) \
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{ \
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return atomic##prefix##_##func_op##_return(v) comp_op I; \
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}
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ATOMIC_OP(inc_and_test, inc, ==, 0, )
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ATOMIC_OP(dec_and_test, dec, ==, 0, )
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#ifndef CONFIG_GENERIC_ATOMIC64
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ATOMIC_OP(inc_and_test, inc, ==, 0, 64)
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ATOMIC_OP(dec_and_test, dec, ==, 0, 64)
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#endif
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#undef ATOMIC_OP
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/* This is required to provide a barrier on success. */
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static __always_inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0:\n\t"
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"lr.w.aqrl %[p], %[c]\n\t"
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"beq %[p], %[u], 1f\n\t"
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"add %[rc], %[p], %[a]\n\t"
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"sc.w.aqrl %[rc], %[rc], %[c]\n\t"
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"bnez %[rc], 0b\n\t"
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"1:"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long __atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long prev, rc;
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__asm__ __volatile__ (
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"0:\n\t"
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"lr.d.aqrl %[p], %[c]\n\t"
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"beq %[p], %[u], 1f\n\t"
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"add %[rc], %[p], %[a]\n\t"
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"sc.d.aqrl %[rc], %[rc], %[c]\n\t"
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"bnez %[rc], 0b\n\t"
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"1:"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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static __always_inline int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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return __atomic64_add_unless(v, a, u) != u;
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}
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#endif
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/*
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* The extra atomic operations that are constructed from one of the core
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* LR/SC-based operations above.
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*/
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static __always_inline int atomic_inc_not_zero(atomic_t *v)
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{
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return __atomic_add_unless(v, 1, 0);
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}
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long atomic64_inc_not_zero(atomic64_t *v)
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{
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return atomic64_add_unless(v, 1, 0);
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}
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#endif
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/*
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* atomic_{cmp,}xchg is required to have exactly the same ordering semantics as
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* {cmp,}xchg and the operations that return, so they need a barrier. We just
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* use the other implementations directly.
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*/
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#define ATOMIC_OP(c_t, prefix, c_or, size, asm_or) \
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static __always_inline c_t atomic##prefix##_cmpxchg##c_or(atomic##prefix##_t *v, c_t o, c_t n) \
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{ \
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return __cmpxchg(&(v->counter), o, n, size, asm_or, asm_or); \
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} \
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static __always_inline c_t atomic##prefix##_xchg##c_or(atomic##prefix##_t *v, c_t n) \
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{ \
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return __xchg(n, &(v->counter), size, asm_or); \
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}
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#ifdef CONFIG_GENERIC_ATOMIC64
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#define ATOMIC_OPS(c_or, asm_or) \
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ATOMIC_OP( int, , c_or, 4, asm_or)
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#else
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#define ATOMIC_OPS(c_or, asm_or) \
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ATOMIC_OP( int, , c_or, 4, asm_or) \
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ATOMIC_OP(long, 64, c_or, 8, asm_or)
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#endif
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ATOMIC_OPS( , .aqrl)
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ATOMIC_OPS(_acquire, .aq)
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ATOMIC_OPS(_release, .rl)
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ATOMIC_OPS(_relaxed, )
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#undef ATOMIC_OPS
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#undef ATOMIC_OP
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static __always_inline int atomic_sub_if_positive(atomic_t *v, int offset)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0:\n\t"
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"lr.w.aqrl %[p], %[c]\n\t"
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"sub %[rc], %[p], %[o]\n\t"
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"bltz %[rc], 1f\n\t"
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"sc.w.aqrl %[rc], %[rc], %[c]\n\t"
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"bnez %[rc], 0b\n\t"
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"1:"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [o]"r" (offset)
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: "memory");
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return prev - offset;
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}
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#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1)
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline long atomic64_sub_if_positive(atomic64_t *v, int offset)
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{
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long prev, rc;
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__asm__ __volatile__ (
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"0:\n\t"
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"lr.d.aqrl %[p], %[c]\n\t"
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"sub %[rc], %[p], %[o]\n\t"
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"bltz %[rc], 1f\n\t"
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"sc.d.aqrl %[rc], %[rc], %[c]\n\t"
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"bnez %[rc], 0b\n\t"
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"1:"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [o]"r" (offset)
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: "memory");
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return prev - offset;
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}
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#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(v, 1)
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#endif
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#endif /* _ASM_RISCV_ATOMIC_H */
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