Merge branches 'ib-mfd-iio-input-5.1', 'ib-mfd-input-watchdog-5.1' and 'ib-mfd-platform-5.1' into ibs-for-mfd-merged
This commit is contained in:
Lee Jones
@@ -281,16 +281,6 @@ int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev,
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int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev,
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struct cros_ec_command *msg);
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/**
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* cros_ec_remove() - Remove a ChromeOS EC.
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* @ec_dev: Device to register.
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*
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* Call this to deregister a ChromeOS EC, then clean up any private data.
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*
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* Return: 0 on success or negative error code.
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*/
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int cros_ec_remove(struct cros_ec_device *ec_dev);
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/**
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* cros_ec_register() - Register a new ChromeOS EC, using the provided info.
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* @ec_dev: Device to register.
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@@ -335,15 +325,4 @@ int cros_ec_get_next_event(struct cros_ec_device *ec_dev, bool *wake_event);
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*/
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u32 cros_ec_get_host_event(struct cros_ec_device *ec_dev);
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/* sysfs stuff */
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extern struct attribute_group cros_ec_attr_group;
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extern struct attribute_group cros_ec_lightbar_attr_group;
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extern struct attribute_group cros_ec_vbc_attr_group;
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/* debugfs stuff */
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int cros_ec_debugfs_init(struct cros_ec_dev *ec);
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void cros_ec_debugfs_remove(struct cros_ec_dev *ec);
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void cros_ec_debugfs_suspend(struct cros_ec_dev *ec);
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void cros_ec_debugfs_resume(struct cros_ec_dev *ec);
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#endif /* __LINUX_MFD_CROS_EC_H */
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@@ -2790,6 +2790,100 @@ struct ec_response_battery_vendor_param {
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uint32_t value;
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} __packed;
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/*****************************************************************************/
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/* Commands for I2S recording on audio codec. */
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#define EC_CMD_CODEC_I2S 0x00BC
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enum ec_codec_i2s_subcmd {
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EC_CODEC_SET_SAMPLE_DEPTH = 0x0,
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EC_CODEC_SET_GAIN = 0x1,
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EC_CODEC_GET_GAIN = 0x2,
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EC_CODEC_I2S_ENABLE = 0x3,
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EC_CODEC_I2S_SET_CONFIG = 0x4,
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EC_CODEC_I2S_SET_TDM_CONFIG = 0x5,
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EC_CODEC_I2S_SET_BCLK = 0x6,
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};
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enum ec_sample_depth_value {
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EC_CODEC_SAMPLE_DEPTH_16 = 0,
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EC_CODEC_SAMPLE_DEPTH_24 = 1,
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};
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enum ec_i2s_config {
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EC_DAI_FMT_I2S = 0,
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EC_DAI_FMT_RIGHT_J = 1,
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EC_DAI_FMT_LEFT_J = 2,
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EC_DAI_FMT_PCM_A = 3,
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EC_DAI_FMT_PCM_B = 4,
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EC_DAI_FMT_PCM_TDM = 5,
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};
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struct ec_param_codec_i2s {
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/*
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* enum ec_codec_i2s_subcmd
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*/
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uint8_t cmd;
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union {
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/*
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* EC_CODEC_SET_SAMPLE_DEPTH
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* Value should be one of ec_sample_depth_value.
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*/
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uint8_t depth;
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/*
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* EC_CODEC_SET_GAIN
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* Value should be 0~43 for both channels.
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*/
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struct ec_param_codec_i2s_set_gain {
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uint8_t left;
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uint8_t right;
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} __packed gain;
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/*
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* EC_CODEC_I2S_ENABLE
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* 1 to enable, 0 to disable.
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*/
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uint8_t i2s_enable;
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/*
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* EC_CODEC_I2S_SET_COFNIG
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* Value should be one of ec_i2s_config.
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*/
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uint8_t i2s_config;
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/*
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* EC_CODEC_I2S_SET_TDM_CONFIG
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* Value should be one of ec_i2s_config.
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*/
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struct ec_param_codec_i2s_tdm {
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/*
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* 0 to 496
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*/
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int16_t ch0_delay;
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/*
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* -1 to 496
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*/
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int16_t ch1_delay;
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uint8_t adjacent_to_ch0;
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uint8_t adjacent_to_ch1;
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} __packed tdm_param;
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/*
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* EC_CODEC_I2S_SET_BCLK
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*/
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uint32_t bclk;
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};
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} __packed;
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/*
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* For subcommand EC_CODEC_GET_GAIN.
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*/
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struct ec_response_codec_gain {
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uint8_t left;
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uint8_t right;
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} __packed;
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/*****************************************************************************/
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/* System commands */
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@@ -41,7 +41,7 @@
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#define TCU_TCSR_PRESCALE_LSB 3
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#define TCU_TCSR_PRESCALE_MASK 0x38
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#define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown abruptly 1: gracefully */
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#define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown gracefully 1: abruptly */
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#define TCU_TCSR_PWM_INITL_HIGH BIT(8) /* Sets the initial output level */
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#define TCU_TCSR_PWM_EN BIT(7) /* PWM pin output enable */
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@@ -15,6 +15,7 @@
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/madera/pdata.h>
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#include <linux/mutex.h>
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#include <linux/notifier.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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@@ -37,6 +38,8 @@ enum madera_type {
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#define MADERA_MAX_MICBIAS 4
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#define MADERA_MAX_HP_OUTPUT 3
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/* Notifier events */
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#define MADERA_NOTIFY_VOICE_TRIGGER 0x1
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#define MADERA_NOTIFY_HPDET 0x2
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@@ -183,6 +186,10 @@ struct madera {
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unsigned int num_childbias[MADERA_MAX_MICBIAS];
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struct snd_soc_dapm_context *dapm;
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struct mutex dapm_ptr_lock;
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unsigned int hp_ena;
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bool out_clamp[MADERA_MAX_HP_OUTPUT];
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bool out_shorted[MADERA_MAX_HP_OUTPUT];
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struct blocking_notifier_head notifier;
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};
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212
include/linux/mfd/stpmic1.h
Normal file
212
include/linux/mfd/stpmic1.h
Normal file
@@ -0,0 +1,212 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Philippe Peurichard <philippe.peurichard@st.com>,
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* Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
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*/
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#ifndef __LINUX_MFD_STPMIC1_H
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#define __LINUX_MFD_STPMIC1_H
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#define TURN_ON_SR 0x1
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#define TURN_OFF_SR 0x2
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#define ICC_LDO_TURN_OFF_SR 0x3
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#define ICC_BUCK_TURN_OFF_SR 0x4
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#define RREQ_STATE_SR 0x5
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#define VERSION_SR 0x6
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#define SWOFF_PWRCTRL_CR 0x10
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#define PADS_PULL_CR 0x11
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#define BUCKS_PD_CR 0x12
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#define LDO14_PD_CR 0x13
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#define LDO56_VREF_PD_CR 0x14
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#define VBUS_DET_VIN_CR 0x15
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#define PKEY_TURNOFF_CR 0x16
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#define BUCKS_MASK_RANK_CR 0x17
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#define BUCKS_MASK_RESET_CR 0x18
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#define LDOS_MASK_RANK_CR 0x19
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#define LDOS_MASK_RESET_CR 0x1A
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#define WCHDG_CR 0x1B
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#define WCHDG_TIMER_CR 0x1C
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#define BUCKS_ICCTO_CR 0x1D
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#define LDOS_ICCTO_CR 0x1E
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#define BUCK1_ACTIVE_CR 0x20
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#define BUCK2_ACTIVE_CR 0x21
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#define BUCK3_ACTIVE_CR 0x22
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#define BUCK4_ACTIVE_CR 0x23
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#define VREF_DDR_ACTIVE_CR 0x24
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#define LDO1_ACTIVE_CR 0x25
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#define LDO2_ACTIVE_CR 0x26
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#define LDO3_ACTIVE_CR 0x27
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#define LDO4_ACTIVE_CR 0x28
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#define LDO5_ACTIVE_CR 0x29
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#define LDO6_ACTIVE_CR 0x2A
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#define BUCK1_STDBY_CR 0x30
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#define BUCK2_STDBY_CR 0x31
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#define BUCK3_STDBY_CR 0x32
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#define BUCK4_STDBY_CR 0x33
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#define VREF_DDR_STDBY_CR 0x34
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#define LDO1_STDBY_CR 0x35
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#define LDO2_STDBY_CR 0x36
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#define LDO3_STDBY_CR 0x37
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#define LDO4_STDBY_CR 0x38
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#define LDO5_STDBY_CR 0x39
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#define LDO6_STDBY_CR 0x3A
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#define BST_SW_CR 0x40
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#define INT_PENDING_R1 0x50
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#define INT_PENDING_R2 0x51
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#define INT_PENDING_R3 0x52
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#define INT_PENDING_R4 0x53
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#define INT_DBG_LATCH_R1 0x60
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#define INT_DBG_LATCH_R2 0x61
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#define INT_DBG_LATCH_R3 0x62
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#define INT_DBG_LATCH_R4 0x63
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#define INT_CLEAR_R1 0x70
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#define INT_CLEAR_R2 0x71
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#define INT_CLEAR_R3 0x72
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#define INT_CLEAR_R4 0x73
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#define INT_MASK_R1 0x80
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#define INT_MASK_R2 0x81
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#define INT_MASK_R3 0x82
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#define INT_MASK_R4 0x83
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#define INT_SET_MASK_R1 0x90
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#define INT_SET_MASK_R2 0x91
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#define INT_SET_MASK_R3 0x92
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#define INT_SET_MASK_R4 0x93
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#define INT_CLEAR_MASK_R1 0xA0
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#define INT_CLEAR_MASK_R2 0xA1
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#define INT_CLEAR_MASK_R3 0xA2
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#define INT_CLEAR_MASK_R4 0xA3
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#define INT_SRC_R1 0xB0
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#define INT_SRC_R2 0xB1
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#define INT_SRC_R3 0xB2
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#define INT_SRC_R4 0xB3
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#define PMIC_MAX_REGISTER_ADDRESS INT_SRC_R4
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#define STPMIC1_PMIC_NUM_IRQ_REGS 4
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#define TURN_OFF_SR_ICC_EVENT 0x08
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#define LDO_VOLTAGE_MASK GENMASK(6, 2)
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#define BUCK_VOLTAGE_MASK GENMASK(7, 2)
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#define LDO_BUCK_VOLTAGE_SHIFT 2
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#define LDO_ENABLE_MASK BIT(0)
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#define BUCK_ENABLE_MASK BIT(0)
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#define BUCK_HPLP_ENABLE_MASK BIT(1)
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#define BUCK_HPLP_SHIFT 1
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#define STDBY_ENABLE_MASK BIT(0)
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#define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)
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#define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)
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#define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)
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#define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)
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#define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)
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#define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)
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#define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)
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#define BUCK1_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK1_PULL_DOWN_MASK BIT(0)
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#define BUCK2_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK2_PULL_DOWN_MASK BIT(2)
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#define BUCK3_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK3_PULL_DOWN_MASK BIT(4)
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#define BUCK4_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK4_PULL_DOWN_MASK BIT(6)
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#define LDO1_PULL_DOWN_REG LDO14_PD_CR
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#define LDO1_PULL_DOWN_MASK BIT(0)
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#define LDO2_PULL_DOWN_REG LDO14_PD_CR
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#define LDO2_PULL_DOWN_MASK BIT(2)
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#define LDO3_PULL_DOWN_REG LDO14_PD_CR
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#define LDO3_PULL_DOWN_MASK BIT(4)
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#define LDO4_PULL_DOWN_REG LDO14_PD_CR
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#define LDO4_PULL_DOWN_MASK BIT(6)
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#define LDO5_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define LDO5_PULL_DOWN_MASK BIT(0)
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#define LDO6_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define LDO6_PULL_DOWN_MASK BIT(2)
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#define VREF_DDR_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define VREF_DDR_PULL_DOWN_MASK BIT(4)
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#define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)
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#define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0)
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#define LDO_BYPASS_MASK BIT(7)
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/* Main PMIC Control Register
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* SWOFF_PWRCTRL_CR
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* Address : 0x10
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*/
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#define ICC_EVENT_ENABLED BIT(4)
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#define PWRCTRL_POLARITY_HIGH BIT(3)
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#define PWRCTRL_PIN_VALID BIT(2)
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#define RESTART_REQUEST_ENABLED BIT(1)
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#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
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/* Main PMIC PADS Control Register
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* PADS_PULL_CR
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* Address : 0x11
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*/
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#define WAKEUP_DETECTOR_DISABLED BIT(4)
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#define PWRCTRL_PD_ACTIVE BIT(3)
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#define PWRCTRL_PU_ACTIVE BIT(2)
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#define WAKEUP_PD_ACTIVE BIT(1)
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#define PONKEY_PU_INACTIVE BIT(0)
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/* Main PMIC VINLOW Control Register
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* VBUS_DET_VIN_CRC DMSC
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* Address : 0x15
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*/
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#define SWIN_DETECTOR_ENABLED BIT(7)
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#define SWOUT_DETECTOR_ENABLED BIT(6)
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#define VINLOW_ENABLED BIT(0)
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#define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
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/* USB Control Register
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* Address : 0x40
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*/
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#define BOOST_OVP_DISABLED BIT(7)
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#define VBUS_OTG_DETECTION_DISABLED BIT(6)
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#define SW_OUT_DISCHARGE BIT(5)
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#define VBUS_OTG_DISCHARGE BIT(4)
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#define OCP_LIMIT_HIGH BIT(3)
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#define SWIN_SWOUT_ENABLED BIT(2)
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#define USBSW_OTG_SWITCH_ENABLED BIT(1)
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#define BOOST_ENABLED BIT(0)
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/* PKEY_TURNOFF_CR
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* Address : 0x16
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*/
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#define PONKEY_PWR_OFF BIT(7)
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#define PONKEY_CC_FLAG_CLEAR BIT(6)
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#define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0)
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#define PONKEY_TURNOFF_MASK GENMASK(7, 0)
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/*
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* struct stpmic1 - stpmic1 master device for sub-drivers
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* @dev: master device of the chip (can be used to access platform data)
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* @irq: main IRQ number
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* @regmap_irq_chip_data: irq chip data
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*/
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struct stpmic1 {
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struct device *dev;
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struct regmap *regmap;
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int irq;
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struct regmap_irq_chip_data *irq_data;
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};
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#endif /* __LINUX_MFD_STPMIC1_H */
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@@ -78,6 +78,8 @@
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#define STEPCONFIG_YNN BIT(8)
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#define STEPCONFIG_XNP BIT(9)
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#define STEPCONFIG_YPN BIT(10)
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#define STEPCONFIG_RFP(val) ((val) << 12)
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#define STEPCONFIG_RFP_VREFP (0x3 << 12)
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#define STEPCONFIG_INM_MASK (0xF << 15)
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#define STEPCONFIG_INM(val) ((val) << 15)
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#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
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@@ -86,6 +88,8 @@
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#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
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#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
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#define STEPCONFIG_FIFO1 BIT(26)
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#define STEPCONFIG_RFM(val) ((val) << 23)
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#define STEPCONFIG_RFM_VREFN (0x3 << 23)
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/* Delay register */
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#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
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@@ -79,7 +79,7 @@
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/* Some controllers have a CBSY bit */
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#define TMIO_MMC_HAVE_CBSY BIT(11)
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/* Some controllers that support HS400 use use 4 taps while others use 8. */
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/* Some controllers that support HS400 use 4 taps while others use 8. */
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#define TMIO_MMC_HAVE_4TAP_HS400 BIT(13)
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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||||
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||||
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