ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
Clean all #ifdef's added to common clock code. This code is no longer needed due to migration to the common clock framework. Signed-off-by: Mike Turquette <mturquette@ti.com> [paul@pwsan.com: clean up new ifdefs added in clockdomain.c] Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Mike Turquette
committed by
Paul Walmsley
Paul Walmsley
parent
f51e0f9862
commit
f9ae32a74f
@@ -20,6 +20,7 @@
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#include <linux/list.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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struct omap_clk {
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u16 cpu;
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@@ -52,9 +53,6 @@ struct omap_clk {
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#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
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#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
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#ifdef CONFIG_COMMON_CLK
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#include <linux/clk-provider.h>
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struct clockdomain;
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#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
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@@ -134,48 +132,6 @@ struct clockdomain;
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}; \
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DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
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#else
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struct module;
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struct clk;
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struct clockdomain;
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/* Temporary, needed during the common clock framework conversion */
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#define __clk_get_name(clk) (clk->name)
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#define __clk_get_parent(clk) (clk->parent)
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#define __clk_get_rate(clk) (clk->rate)
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/**
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* struct clkops - some clock function pointers
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* @enable: fn ptr that enables the current clock in hardware
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* @disable: fn ptr that enables the current clock in hardware
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* @find_idlest: function returning the IDLEST register for the clock's IP blk
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* @find_companion: function returning the "companion" clk reg for the clock
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* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
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* @deny_idle: fn ptr that disables autoidle for the current clock in hardware
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*
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* A "companion" clk is an accompanying clock to the one being queried
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* that must be enabled for the IP module connected to the clock to
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* become accessible by the hardware. Neither @find_idlest nor
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* @find_companion should be needed; that information is IP
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* block-specific; the hwmod code has been created to handle this, but
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* until hwmod data is ready and drivers have been converted to use PM
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* runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
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* @find_companion must, unfortunately, remain.
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*/
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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void (*find_idlest)(struct clk *, void __iomem **,
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u8 *, u8 *);
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void (*find_companion)(struct clk *, void __iomem **,
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u8 *);
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void (*allow_idle)(struct clk *);
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void (*deny_idle)(struct clk *);
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};
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#endif
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/* struct clksel_rate.flags possibilities */
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#define RATE_IN_242X (1 << 0)
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#define RATE_IN_243X (1 << 1)
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@@ -314,7 +270,6 @@ struct dpll_data {
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#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
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#define CLOCK_CLKOUTX2 (1 << 5)
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#ifdef CONFIG_COMMON_CLK
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/**
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* struct clk_hw_omap - OMAP struct clk
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* @node: list_head connecting this clock into the full clock list
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@@ -367,114 +322,6 @@ struct clk_hw_omap_ops {
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unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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#else
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/**
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* struct clk - OMAP struct clk
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* @node: list_head connecting this clock into the full clock list
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* @ops: struct clkops * for this clock
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* @name: the name of the clock in the hardware (used in hwmod data and debug)
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* @parent: pointer to this clock's parent struct clk
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* @children: list_head connecting to the child clks' @sibling list_heads
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* @sibling: list_head connecting this clk to its parent clk's @children
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* @rate: current clock rate
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* @enable_reg: register to write to enable the clock (see @enable_bit)
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* @recalc: fn ptr that returns the clock's current rate
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* @set_rate: fn ptr that can change the clock's current rate
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* @round_rate: fn ptr that can round the clock's current rate
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* @init: fn ptr to do clock-specific initialization
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
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* @usecount: number of users that have requested this clock to be enabled
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* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
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* @flags: see "struct clk.flags possibilities" above
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* @clksel_reg: for clksel clks, register va containing src/divisor select
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* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
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* @clksel: for clksel clks, pointer to struct clksel for this clock
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* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
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* @clkdm_name: clockdomain name that this clock is contained in
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* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
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* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
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* @src_offset: bitshift for source selection bitfield (OMAP1 only)
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*
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* XXX @rate_offset, @src_offset should probably be removed and OMAP1
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* clock code converted to use clksel.
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*
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* XXX @usecount is poorly named. It should be "enable_count" or
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* something similar. "users" in the description refers to kernel
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* code (core code or drivers) that have called clk_enable() and not
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* yet called clk_disable(); the usecount of parent clocks is also
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* incremented by the clock code when clk_enable() is called on child
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* clocks and decremented by the clock code when clk_disable() is
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* called on child clocks.
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*
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* XXX @clkdm, @usecount, @children, @sibling should be marked for
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* internal use only.
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*
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* @children and @sibling are used to optimize parent-to-child clock
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* tree traversals. (child-to-parent traversals use @parent.)
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*
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* XXX The notion of the clock's current rate probably needs to be
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* separated from the clock's target rate.
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*/
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struct clk {
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struct list_head node;
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const struct clkops *ops;
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const char *name;
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struct clk *parent;
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struct list_head children;
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struct list_head sibling; /* node for children */
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unsigned long rate;
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void __iomem *enable_reg;
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unsigned long (*recalc)(struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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u8 enable_bit;
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s8 usecount;
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u8 fixed_div;
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u8 flags;
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void __iomem *clksel_reg;
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u32 clksel_mask;
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const struct clksel *clksel;
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struct dpll_data *dpll_data;
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const char *clkdm_name;
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struct clockdomain *clkdm;
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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struct dentry *dent; /* For visible tree hierarchy */
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#endif
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};
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struct clk_functions {
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int (*clk_enable)(struct clk *clk);
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void (*clk_disable)(struct clk *clk);
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long (*clk_round_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_parent)(struct clk *clk, struct clk *parent);
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void (*clk_allow_idle)(struct clk *clk);
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void (*clk_deny_idle)(struct clk *clk);
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void (*clk_disable_unused)(struct clk *clk);
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};
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extern int mpurate;
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extern int clk_init(struct clk_functions *custom_clocks);
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extern void clk_preinit(struct clk *clk);
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extern int clk_register(struct clk *clk);
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extern void clk_reparent(struct clk *child, struct clk *parent);
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extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern void recalculate_root_clocks(void);
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extern unsigned long followparent_recalc(struct clk *clk);
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extern void clk_enable_init_clocks(void);
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unsigned long omap_fixed_divisor_recalc(struct clk *clk);
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extern struct clk *omap_clk_get_by_name(const char *name);
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extern int omap_clk_enable_autoidle_all(void);
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extern int omap_clk_disable_autoidle_all(void);
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extern const struct clkops clkops_null;
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extern struct clk dummy_ck;
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#endif /* CONFIG_COMMON_CLK */
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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@@ -505,15 +352,6 @@ extern struct clk dummy_ck;
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/* DPLL Type and DCO Selection Flags */
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#define DPLL_J_TYPE 0x1
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#ifndef CONFIG_COMMON_CLK
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int omap2_clk_enable(struct clk *clk);
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void omap2_clk_disable(struct clk *clk);
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
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#endif /* CONFIG_COMMON_CLK */
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#ifdef CONFIG_COMMON_CLK
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long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
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@@ -534,37 +372,11 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
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unsigned long target_rate,
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unsigned long *parent_rate);
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#else
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap3_dpll_recalc(struct clk *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk *clk);
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void omap3_dpll_allow_idle(struct clk *clk);
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void omap3_dpll_deny_idle(struct clk *clk);
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u32 omap3_dpll_autoidle_read(struct clk *clk);
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
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int omap3_noncore_dpll_enable(struct clk *clk);
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void omap3_noncore_dpll_disable(struct clk *clk);
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int omap4_dpllmx_gatectrl_read(struct clk *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk *clk);
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void omap4_dpllmx_deny_gatectrl(struct clk *clk);
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long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
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#endif
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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void omap2_clk_disable_unused(struct clk *clk);
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#else
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#define omap2_clk_disable_unused NULL
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#endif
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#ifdef CONFIG_COMMON_CLK
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void omap2_init_clk_clkdm(struct clk_hw *clk);
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#else
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void omap2_init_clk_clkdm(struct clk *clk);
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#endif
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void __init omap2_clk_disable_clkdm_control(void);
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/* clkt_clksel.c public functions */
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#ifdef CONFIG_COMMON_CLK
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u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
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unsigned long target_rate,
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u32 *new_div);
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@@ -575,29 +387,14 @@ long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
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int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
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#else
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u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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u32 *new_div);
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void omap2_init_clksel_parent(struct clk *clk);
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unsigned long omap2_clksel_recalc(struct clk *clk);
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long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
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#endif
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/* clkt_iclk.c public functions */
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extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
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extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
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#ifdef CONFIG_COMMON_CLK
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u8 omap2_init_dpll_parent(struct clk_hw *hw);
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
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#else
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u32 omap2_get_dpll_rate(struct clk *clk);
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void omap2_init_dpll_parent(struct clk *clk);
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#endif
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#ifdef CONFIG_COMMON_CLK
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int omap2_dflt_clk_enable(struct clk_hw *hw);
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void omap2_dflt_clk_disable(struct clk_hw *hw);
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int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
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@@ -611,14 +408,6 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk);
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int omap2_clk_enable_autoidle_all(void);
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int omap2_clk_disable_autoidle_all(void);
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void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
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#else
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int omap2_dflt_clk_enable(struct clk *clk);
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void omap2_dflt_clk_disable(struct clk *clk);
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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u8 *other_bit);
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void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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#endif
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int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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@@ -665,17 +454,9 @@ extern const struct clksel_rate div_1_3_rates[];
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extern const struct clksel_rate div_1_4_rates[];
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extern const struct clksel_rate div31_1to31_rates[];
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#ifndef CONFIG_COMMON_CLK
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/* clocks shared between various OMAP SoCs */
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extern struct clk virt_19200000_ck;
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extern struct clk virt_26000000_ck;
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#endif
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extern int am33xx_clk_init(void);
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#ifdef CONFIG_COMMON_CLK
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extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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#endif
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#endif
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