IB/qib: Add new qib driver for QLogic PCIe InfiniBand adapters
Add a low-level IB driver for QLogic PCIe adapters. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Ralph Campbell
committed by
Roland Dreier
Roland Dreier
parent
9a6edb60ec
commit
f931551baf
498
drivers/infiniband/hw/qib/qib_twsi.c
Normal file
498
drivers/infiniband/hw/qib/qib_twsi.c
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@@ -0,0 +1,498 @@
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/*
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* Copyright (c) 2006, 2007, 2008, 2009 QLogic Corporation. All rights reserved.
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* Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include "qib.h"
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/*
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* QLogic_IB "Two Wire Serial Interface" driver.
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* Originally written for a not-quite-i2c serial eeprom, which is
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* still used on some supported boards. Later boards have added a
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* variety of other uses, most board-specific, so teh bit-boffing
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* part has been split off to this file, while the other parts
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* have been moved to chip-specific files.
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*
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* We have also dropped all pretense of fully generic (e.g. pretend
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* we don't know whether '1' is the higher voltage) interface, as
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* the restrictions of the generic i2c interface (e.g. no access from
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* driver itself) make it unsuitable for this use.
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*/
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#define READ_CMD 1
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#define WRITE_CMD 0
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/**
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* i2c_wait_for_writes - wait for a write
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* @dd: the qlogic_ib device
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*
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* We use this instead of udelay directly, so we can make sure
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* that previous register writes have been flushed all the way
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* to the chip. Since we are delaying anyway, the cost doesn't
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* hurt, and makes the bit twiddling more regular
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*/
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static void i2c_wait_for_writes(struct qib_devdata *dd)
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{
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/*
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* implicit read of EXTStatus is as good as explicit
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* read of scratch, if all we want to do is flush
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* writes.
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*/
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dd->f_gpio_mod(dd, 0, 0, 0);
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rmb(); /* inlined, so prevent compiler reordering */
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}
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/*
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* QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
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* for "almost compliant" modules
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*/
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#define SCL_WAIT_USEC 1000
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/* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
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* Should be 20, but some chips need more.
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*/
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#define TWSI_BUF_WAIT_USEC 60
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static void scl_out(struct qib_devdata *dd, u8 bit)
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{
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u32 mask;
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udelay(1);
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mask = 1UL << dd->gpio_scl_num;
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/* SCL is meant to be bare-drain, so never set "OUT", just DIR */
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dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
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/*
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* Allow for slow slaves by simple
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* delay for falling edge, sampling on rise.
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*/
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if (!bit)
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udelay(2);
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else {
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int rise_usec;
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for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
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if (mask & dd->f_gpio_mod(dd, 0, 0, 0))
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break;
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udelay(2);
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}
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if (rise_usec <= 0)
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qib_dev_err(dd, "SCL interface stuck low > %d uSec\n",
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SCL_WAIT_USEC);
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}
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i2c_wait_for_writes(dd);
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}
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static void sda_out(struct qib_devdata *dd, u8 bit)
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{
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u32 mask;
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mask = 1UL << dd->gpio_sda_num;
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/* SDA is meant to be bare-drain, so never set "OUT", just DIR */
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dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask);
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i2c_wait_for_writes(dd);
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udelay(2);
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}
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static u8 sda_in(struct qib_devdata *dd, int wait)
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{
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int bnum;
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u32 read_val, mask;
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bnum = dd->gpio_sda_num;
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mask = (1UL << bnum);
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/* SDA is meant to be bare-drain, so never set "OUT", just DIR */
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dd->f_gpio_mod(dd, 0, 0, mask);
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read_val = dd->f_gpio_mod(dd, 0, 0, 0);
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if (wait)
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i2c_wait_for_writes(dd);
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return (read_val & mask) >> bnum;
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}
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/**
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* i2c_ackrcv - see if ack following write is true
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* @dd: the qlogic_ib device
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*/
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static int i2c_ackrcv(struct qib_devdata *dd)
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{
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u8 ack_received;
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/* AT ENTRY SCL = LOW */
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/* change direction, ignore data */
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ack_received = sda_in(dd, 1);
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scl_out(dd, 1);
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ack_received = sda_in(dd, 1) == 0;
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scl_out(dd, 0);
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return ack_received;
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}
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static void stop_cmd(struct qib_devdata *dd);
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/**
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* rd_byte - read a byte, sending STOP on last, else ACK
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* @dd: the qlogic_ib device
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*
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* Returns byte shifted out of device
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*/
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static int rd_byte(struct qib_devdata *dd, int last)
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{
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int bit_cntr, data;
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data = 0;
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for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
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data <<= 1;
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scl_out(dd, 1);
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data |= sda_in(dd, 0);
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scl_out(dd, 0);
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}
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if (last) {
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scl_out(dd, 1);
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stop_cmd(dd);
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} else {
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sda_out(dd, 0);
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scl_out(dd, 1);
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scl_out(dd, 0);
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sda_out(dd, 1);
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}
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return data;
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}
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/**
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* wr_byte - write a byte, one bit at a time
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* @dd: the qlogic_ib device
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* @data: the byte to write
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*
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* Returns 0 if we got the following ack, otherwise 1
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*/
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static int wr_byte(struct qib_devdata *dd, u8 data)
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{
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int bit_cntr;
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u8 bit;
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for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
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bit = (data >> bit_cntr) & 1;
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sda_out(dd, bit);
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scl_out(dd, 1);
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scl_out(dd, 0);
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}
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return (!i2c_ackrcv(dd)) ? 1 : 0;
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}
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/*
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* issue TWSI start sequence:
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* (both clock/data high, clock high, data low while clock is high)
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*/
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static void start_seq(struct qib_devdata *dd)
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{
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sda_out(dd, 1);
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scl_out(dd, 1);
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sda_out(dd, 0);
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udelay(1);
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scl_out(dd, 0);
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}
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/**
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* stop_seq - transmit the stop sequence
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* @dd: the qlogic_ib device
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*
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* (both clock/data low, clock high, data high while clock is high)
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*/
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static void stop_seq(struct qib_devdata *dd)
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{
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scl_out(dd, 0);
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sda_out(dd, 0);
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scl_out(dd, 1);
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sda_out(dd, 1);
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}
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/**
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* stop_cmd - transmit the stop condition
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* @dd: the qlogic_ib device
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*
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* (both clock/data low, clock high, data high while clock is high)
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*/
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static void stop_cmd(struct qib_devdata *dd)
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{
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stop_seq(dd);
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udelay(TWSI_BUF_WAIT_USEC);
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}
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/**
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* qib_twsi_reset - reset I2C communication
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* @dd: the qlogic_ib device
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*/
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int qib_twsi_reset(struct qib_devdata *dd)
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{
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int clock_cycles_left = 9;
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int was_high = 0;
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u32 pins, mask;
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/* Both SCL and SDA should be high. If not, there
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* is something wrong.
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*/
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mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num);
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/*
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* Force pins to desired innocuous state.
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* This is the default power-on state with out=0 and dir=0,
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* So tri-stated and should be floating high (barring HW problems)
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*/
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dd->f_gpio_mod(dd, 0, 0, mask);
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/*
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* Clock nine times to get all listeners into a sane state.
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* If SDA does not go high at any point, we are wedged.
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* One vendor recommends then issuing START followed by STOP.
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* we cannot use our "normal" functions to do that, because
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* if SCL drops between them, another vendor's part will
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* wedge, dropping SDA and keeping it low forever, at the end of
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* the next transaction (even if it was not the device addressed).
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* So our START and STOP take place with SCL held high.
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*/
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while (clock_cycles_left--) {
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scl_out(dd, 0);
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scl_out(dd, 1);
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/* Note if SDA is high, but keep clocking to sync slave */
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was_high |= sda_in(dd, 0);
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}
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if (was_high) {
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/*
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* We saw a high, which we hope means the slave is sync'd.
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* Issue START, STOP, pause for T_BUF.
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*/
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pins = dd->f_gpio_mod(dd, 0, 0, 0);
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if ((pins & mask) != mask)
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qib_dev_err(dd, "GPIO pins not at rest: %d\n",
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pins & mask);
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/* Drop SDA to issue START */
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udelay(1); /* Guarantee .6 uSec setup */
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sda_out(dd, 0);
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udelay(1); /* Guarantee .6 uSec hold */
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/* At this point, SCL is high, SDA low. Raise SDA for STOP */
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sda_out(dd, 1);
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udelay(TWSI_BUF_WAIT_USEC);
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}
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return !was_high;
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}
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#define QIB_TWSI_START 0x100
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#define QIB_TWSI_STOP 0x200
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/* Write byte to TWSI, optionally prefixed with START or suffixed with
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* STOP.
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* returns 0 if OK (ACK received), else != 0
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*/
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static int qib_twsi_wr(struct qib_devdata *dd, int data, int flags)
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{
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int ret = 1;
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if (flags & QIB_TWSI_START)
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start_seq(dd);
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ret = wr_byte(dd, data); /* Leaves SCL low (from i2c_ackrcv()) */
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if (flags & QIB_TWSI_STOP)
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stop_cmd(dd);
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return ret;
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}
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/* Added functionality for IBA7220-based cards */
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#define QIB_TEMP_DEV 0x98
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/*
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* qib_twsi_blk_rd
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* Formerly called qib_eeprom_internal_read, and only used for eeprom,
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* but now the general interface for data transfer from twsi devices.
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* One vestige of its former role is that it recognizes a device
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* QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
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* which responded to all TWSI device codes, interpreting them as
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* address within device. On all other devices found on board handled by
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* this driver, the device is followed by a one-byte "address" which selects
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* the "register" or "offset" within the device from which data should
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* be read.
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*/
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int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr,
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void *buffer, int len)
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{
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int ret;
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u8 *bp = buffer;
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ret = 1;
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if (dev == QIB_TWSI_NO_DEV) {
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/* legacy not-really-I2C */
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addr = (addr << 1) | READ_CMD;
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ret = qib_twsi_wr(dd, addr, QIB_TWSI_START);
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} else {
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/* Actual I2C */
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ret = qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START);
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if (ret) {
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stop_cmd(dd);
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ret = 1;
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goto bail;
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}
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/*
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* SFF spec claims we do _not_ stop after the addr
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* but simply issue a start with the "read" dev-addr.
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* Since we are implicitely waiting for ACK here,
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* we need t_buf (nominally 20uSec) before that start,
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* and cannot rely on the delay built in to the STOP
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*/
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ret = qib_twsi_wr(dd, addr, 0);
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udelay(TWSI_BUF_WAIT_USEC);
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if (ret) {
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qib_dev_err(dd,
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"Failed to write interface read addr %02X\n",
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addr);
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ret = 1;
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goto bail;
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}
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ret = qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START);
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}
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if (ret) {
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stop_cmd(dd);
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ret = 1;
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goto bail;
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}
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/*
|
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* block devices keeps clocking data out as long as we ack,
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* automatically incrementing the address. Some have "pages"
|
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* whose boundaries will not be crossed, but the handling
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* of these is left to the caller, who is in a better
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* position to know.
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*/
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while (len-- > 0) {
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/*
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* Get and store data, sending ACK if length remaining,
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* else STOP
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*/
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*bp++ = rd_byte(dd, !len);
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}
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ret = 0;
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bail:
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return ret;
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}
|
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/*
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* qib_twsi_blk_wr
|
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* Formerly called qib_eeprom_internal_write, and only used for eeprom,
|
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* but now the general interface for data transfer to twsi devices.
|
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* One vestige of its former role is that it recognizes a device
|
||||
* QIB_TWSI_NO_DEV and does the correct operation for the legacy part,
|
||||
* which responded to all TWSI device codes, interpreting them as
|
||||
* address within device. On all other devices found on board handled by
|
||||
* this driver, the device is followed by a one-byte "address" which selects
|
||||
* the "register" or "offset" within the device to which data should
|
||||
* be written.
|
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*/
|
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int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
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const void *buffer, int len)
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{
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int sub_len;
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const u8 *bp = buffer;
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int max_wait_time, i;
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int ret;
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ret = 1;
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|
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while (len > 0) {
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if (dev == QIB_TWSI_NO_DEV) {
|
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if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD,
|
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QIB_TWSI_START)) {
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goto failed_write;
|
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}
|
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} else {
|
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/* Real I2C */
|
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if (qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START))
|
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goto failed_write;
|
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ret = qib_twsi_wr(dd, addr, 0);
|
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if (ret) {
|
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qib_dev_err(dd, "Failed to write interface"
|
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" write addr %02X\n", addr);
|
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goto failed_write;
|
||||
}
|
||||
}
|
||||
|
||||
sub_len = min(len, 4);
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addr += sub_len;
|
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len -= sub_len;
|
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|
||||
for (i = 0; i < sub_len; i++)
|
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if (qib_twsi_wr(dd, *bp++, 0))
|
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goto failed_write;
|
||||
|
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stop_cmd(dd);
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||||
|
||||
/*
|
||||
* Wait for write complete by waiting for a successful
|
||||
* read (the chip replies with a zero after the write
|
||||
* cmd completes, and before it writes to the eeprom.
|
||||
* The startcmd for the read will fail the ack until
|
||||
* the writes have completed. We do this inline to avoid
|
||||
* the debug prints that are in the real read routine
|
||||
* if the startcmd fails.
|
||||
* We also use the proper device address, so it doesn't matter
|
||||
* whether we have real eeprom_dev. Legacy likes any address.
|
||||
*/
|
||||
max_wait_time = 100;
|
||||
while (qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START)) {
|
||||
stop_cmd(dd);
|
||||
if (!--max_wait_time)
|
||||
goto failed_write;
|
||||
}
|
||||
/* now read (and ignore) the resulting byte */
|
||||
rd_byte(dd, 1);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
goto bail;
|
||||
|
||||
failed_write:
|
||||
stop_cmd(dd);
|
||||
ret = 1;
|
||||
|
||||
bail:
|
||||
return ret;
|
||||
}
|
||||
Reference in New Issue
Block a user