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Merge tag 'usb-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Browse Source 
Pull USB/PHY updates from Greg KH:
 "Here is the big USB/PHY driver pull request for 5.1-rc1.

  The usual set of gadget driver updates, phy driver updates, xhci
  updates, and typec additions. Also included in here are a lot of small
  cleanups and fixes and driver updates where needed.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (167 commits)
  wusb: Remove unnecessary static function ckhdid_printf
  usb: core: make default autosuspend delay configurable
  usb: core: Fix typo in description of "authorized_default"
  usb: chipidea: Refactor USB PHY selection and keep a single PHY
  usb: chipidea: Grab the (legacy) USB PHY by phandle first
  usb: chipidea: imx: set power polarity
  dt-bindings: usb: ci-hdrc-usb2: add property power-active-high
  usb: chipidea: imx: remove unused header files
  usb: chipidea: tegra: Fix missed ci_hdrc_remove_device()
  usb: core: add option of only authorizing internal devices
  usb: typec: tps6598x: handle block writes separately with plain-I2C adapters
  usb: xhci: Fix for Enabling USB ROLE SWITCH QUIRK on INTEL_SUNRISEPOINT_LP_XHCI
  usb: xhci: fix build warning - missing prototype
  usb: xhci: dbc: Fixing typo error.
  usb: xhci: remove unused member 'parent' in xhci_regset struct
  xhci: tegra: Prevent error pointer dereference
  USB: serial: option: add Telit ME910 ECM composition
  usb: core: Replace hardcoded check with inline function from usb.h
  usb: core: skip interfaces disabled in devicetree
  usb: typec: mux: remove redundant check on variable match
  ...
This commit is contained in:
Linus Torvalds
2019-03-06 16:48:27 -08:00
parent 67e79a6dc2 1c7cf3d5e1
commit f90d64483e
203 changed files with 2952 additions and 1111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/atmel-sysregs.txt
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@@ -147,6 +147,7 @@ required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
"atmel,<chip>-sfrbu", "syscon"
<chip> can be "sama5d3", "sama5d4" or "sama5d2".
It also can be "microchip,sam9x60-sfr", "syscon".
- reg: Should contain registers location and length
sfr@f0038000 {

21
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
View File

@@ -31,28 +31,7 @@ Required subnodes:
- one subnode per DSI device connected on the DSI bus. Each DSI device should
contain a reg property encoding its virtual channel.
Cadence DPHY
============
Cadence DPHY block.
Required properties:
- compatible: should be set to "cdns,dphy".
- reg: physical base address and length of the DPHY registers.
- clocks: DPHY reference clocks.
- clock-names: must contain "psm" and "pll_ref".
- #phy-cells: must be set to 0.
Example:
dphy0: dphy@fd0e0000{
compatible = "cdns,dphy";
reg = <0x0 0xfd0e0000 0x0 0x1000>;
clocks = <&psm_clk>, <&pll_ref_clk>;
clock-names = "psm", "pll_ref";
#phy-cells = <0>;
};
dsi0: dsi@fd0c0000 {
compatible = "cdns,dsi";
reg = <0x0 0xfd0c0000 0x0 0x1000>;

20
Documentation/devicetree/bindings/phy/cdns,dphy.txt Normal file
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@@ -0,0 +1,20 @@
Cadence DPHY
============
Cadence DPHY block.
Required properties:
- compatible: should be set to "cdns,dphy".
- reg: physical base address and length of the DPHY registers.
- clocks: DPHY reference clocks.
- clock-names: must contain "psm" and "pll_ref".
- #phy-cells: must be set to 0.
Example:
dphy0: dphy@fd0e0000{
compatible = "cdns,dphy";
reg = <0x0 0xfd0e0000 0x0 0x1000>;
clocks = <&psm_clk>, <&pll_ref_clk>;
clock-names = "psm", "pll_ref";
#phy-cells = <0>;
};

65
Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
View File

@@ -1,16 +1,27 @@
mvebu comphy driver
-------------------
MVEBU comphy drivers
--------------------
A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It
provides a number of shared PHYs used by various interfaces (network, sata,
usb, PCIe...).
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 7k/8k (on the CP110)
* Armada 3700
It provides a number of shared PHYs used by various interfaces (network, SATA,
USB, PCIe...).
Required properties:
- compatible: should be "marvell,comphy-cp110"
- reg: should contain the comphy register location and length.
- marvell,system-controller: should contain a phandle to the
system controller node.
- compatible: should be one of:
* "marvell,comphy-cp110" for Armada 7k/8k
* "marvell,comphy-a3700" for Armada 3700
- reg: should contain the COMPHY register(s) location(s) and length(s).
* 1 entry for Armada 7k/8k
* 4 entries for Armada 3700 along with the corresponding reg-names
properties, memory areas are:
* Generic COMPHY registers
* Lane 1 (PCIe/GbE)
* Lane 0 (USB3/GbE)
* Lane 2 (SATA/USB3)
- marvell,system-controller: should contain a phandle to the system
controller node (only for Armada 7k/8k)
- #address-cells: should be 1.
- #size-cells: should be 0.
@@ -18,11 +29,11 @@ A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
- reg: comphy lane number.
- #phy-cells : from the generic phy bindings, must be 1. Defines the
- reg: COMPHY lane number.
- #phy-cells : from the generic PHY bindings, must be 1. Defines the
input port to use for a given comphy lane.
Example:
Examples:
cpm_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
@@ -41,3 +52,33 @@ Example:
#phy-cells = <1>;
};
};
comphy: phy@18300 {
compatible = "marvell,comphy-a3700";
reg = <0x18300 0x300>,
<0x1F000 0x400>,
<0x5C000 0x400>,
<0xe0178 0x8>;
reg-names = "comphy",
"lane1_pcie_gbe",
"lane0_usb3_gbe",
"lane2_sata_usb3";
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
};

38
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt Normal file
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@@ -0,0 +1,38 @@
MVEBU A3700 UTMI PHY
--------------------
USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 3700
On Armada 3700, there are two USB controllers, one is compatible with the USB2
and USB3 specifications and supports OTG. The other one is USB2 compliant and
only supports host mode. Both of these controllers come with a slightly
different UTMI PHY.
Required Properties:
- compatible: Should be one of:
* "marvell,a3700-utmi-host-phy" for the PHY connected to
the USB2 host-only controller.
* "marvell,a3700-utmi-otg-phy" for the PHY connected to
the USB3 and USB2 OTG capable controller.
- reg: PHY IP register range.
- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
region covering registers related to both the host
controller and the PHY.
- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
Example:
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,armada-3700-utmi-host-phy";
reg = <0x5f000 0x800>;
marvell,usb-misc-reg = <&usb2_syscon>;
#phy-cells = <0>;
};
usb2_syscon: system-controller@5f800 {
compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
reg = <0x5f800 0x800>;
};

2
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
View File

@@ -23,6 +23,8 @@ Optional properties:
register files". When set driver will request its
phandle as one companion-grf for some special SoCs
(e.g RV1108).
- extcon : phandle to the extcon device providing the cable state for
the otg phy.
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify host or otg port,

9
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
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@@ -9,6 +9,8 @@ Required properties:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
"qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
"qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
@@ -42,6 +44,10 @@ Required properties:
"aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,msm8998-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,msm8998-qmp-ufs-phy" must contain:
"ref", "ref_aux".
For "qcom,sdm845-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref", "com_aux".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
@@ -61,6 +67,9 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
For "qcom,msm8998-qmp-usb3-phy" must contain
"phy", "common".
For "qcom,msm8998-qmp-ufs-phy": no resets are listed.
For "qcom,sdm845-qmp-usb3-phy" must contain:
"phy", "common".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain:

1
Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
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@@ -6,6 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- compatible: compatible list, contains
"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
"qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
- reg: offset and length of the PHY register set.

2
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
View File

@@ -5,6 +5,8 @@ This file provides information on what the device node for the R-Car generation
Required properties:
- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
SoC.
"renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
SoC.
"renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
SoC.

1
Documentation/devicetree/bindings/phy/ti-phy.txt
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@@ -35,6 +35,7 @@ Required properties:
DRA7x
Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
in DRA7x
Should be "ti,am654-usb2" for the USB2 PHYs on AM654.
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.

1
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
View File

@@ -93,6 +93,7 @@ i.mx specific properties
- over-current-active-low: over current signal polarity is active low.
- over-current-active-high: over current signal polarity is active high.
It's recommended to specify the over current polarity.
- power-active-high: power signal polarity is active high
- external-vbus-divider: enables off-chip resistor divider for Vbus
Example:

24
Documentation/devicetree/bindings/usb/ingenic,jz4740-musb.txt Normal file
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@@ -0,0 +1,24 @@
Ingenic JZ4740 MUSB driver
Required properties:
- compatible: Must be "ingenic,jz4740-musb"
- reg: Address range of the UDC register set
- interrupts: IRQ number related to the UDC hardware
- interrupt-names: must be "mc"
- clocks: phandle to the "udc" clock
- clock-names: must be "udc"
Example:
udc: usb@13040000 {
compatible = "ingenic,jz4740-musb";
reg = <0x13040000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <24>;
interrupt-names = "mc";
clocks = <&cgu JZ4740_CLK_UDC>;
clock-names = "udc";
};

6
Documentation/devicetree/bindings/usb/keystone-usb.txt
View File

@@ -3,7 +3,9 @@ TI Keystone Soc USB Controller
DWC3 GLUE
Required properties:
- compatible: should be "ti,keystone-dwc3".
- compatible: should be
"ti,keystone-dwc3" for Keystone 2 SoCs
"ti,am654-dwc3" for AM654 SoC
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property.
- reg : Address and length of the register set for the USB subsystem on
@@ -21,7 +23,7 @@ SoCs only:
- clock-names: Must be "usb".
The following are mandatory properties for Keystone 2 66AK2G SoCs only:
The following are mandatory properties for 66AK2G and AM654:
- power-domains: Should contain a phandle to a PM domain provider node
and an args specifier containing the USB device id

1
Documentation/devicetree/bindings/usb/qcom,dwc3.txt
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@@ -4,6 +4,7 @@ Required properties:
- compatible: Compatible list, contains
"qcom,dwc3"
"qcom,msm8996-dwc3" for msm8996 SOC.
"qcom,msm8998-dwc3" for msm8998 SOC.
"qcom,sdm845-dwc3" for sdm845 SOC.
- reg: Offset and length of register set for QSCRATCH wrapper
- power-domains: specifies a phandle to PM domain provider node

1
Documentation/devicetree/bindings/usb/renesas_usb3.txt
View File

@@ -3,6 +3,7 @@ Renesas Electronics USB3.0 Peripheral driver
Required properties:
- compatible: Must contain one of the following:
- "renesas,r8a774a1-usb3-peri"
- "renesas,r8a774c0-usb3-peri"
- "renesas,r8a7795-usb3-peri"
- "renesas,r8a7796-usb3-peri"
- "renesas,r8a77965-usb3-peri"

1
Documentation/devicetree/bindings/usb/renesas_usbhs.txt
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@@ -7,6 +7,7 @@ Required properties:
- "renesas,usbhs-r8a7744" for r8a7744 (RZ/G1N) compatible device
- "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device
- "renesas,usbhs-r8a774a1" for r8a774a1 (RZ/G2M) compatible device
- "renesas,usbhs-r8a774c0" for r8a774c0 (RZ/G2E) compatible device
- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
- "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
- "renesas,usbhs-r8a7792" for r8a7792 (R-Car V2H) compatible device

4
Documentation/devicetree/bindings/usb/usb251xb.txt
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@@ -64,6 +64,8 @@ Optional properties :
- power-on-time-ms : Specifies the time it takes from the time the host
initiates the power-on sequence to a port until the port has adequate
power. The value is given in ms in a 0 - 510 range (default is 100ms).
- swap-dx-lanes : Specifies the ports which will swap the differential-pair
(D+/D-), default is not-swapped.
Examples:
usb2512b@2c {
@@ -81,4 +83,6 @@ Examples:
manufacturer = "Foo";
product = "Foo-Bar";
serial = "1234567890A";
/* correct misplaced usb connectors on port 1,2 */
swap-dx-lanes = <1 2>;
};