MIPS: Add support for the M14KEc core.
Signed-off-by: Steven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/ Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:

committed by
John Crispin

parent
127993e561
commit
f8fa4811db
@@ -98,6 +98,9 @@
|
||||
#ifndef cpu_has_rixi
|
||||
#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
|
||||
#endif
|
||||
#ifndef cpu_has_mmips
|
||||
#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
|
||||
#endif
|
||||
#ifndef cpu_has_vtag_icache
|
||||
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
|
||||
#endif
|
||||
|
@@ -96,6 +96,7 @@
|
||||
#define PRID_IMP_1004K 0x9900
|
||||
#define PRID_IMP_1074K 0x9a00
|
||||
#define PRID_IMP_M14KC 0x9c00
|
||||
#define PRID_IMP_M14KEC 0x9e00
|
||||
|
||||
/*
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
|
||||
@@ -264,6 +265,7 @@ enum cpu_type_enum {
|
||||
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
|
||||
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
|
||||
CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
|
||||
CPU_M14KEC,
|
||||
|
||||
/*
|
||||
* MIPS64 class processors
|
||||
@@ -322,6 +324,7 @@ enum cpu_type_enum {
|
||||
#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
|
||||
#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
|
||||
#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
|
||||
#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
|
||||
|
||||
/*
|
||||
* CPU ASE encodings
|
||||
|
@@ -595,6 +595,7 @@
|
||||
#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
|
||||
#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
|
||||
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
|
||||
#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
|
||||
|
||||
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
|
||||
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
|
||||
|
Reference in New Issue
Block a user