xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/nouveau/kms/nv50-: unify set/clr masks

Browse Source 
This is a simplification that'll be used to improve interlock handling.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2018-05-08 20:39:47 +10:00
parent 9d6c2fe191
commit f88bc9d3ec
4 changed files with 20 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/drm/nouveau/dispnv50/atom.h
View File

@@ -105,16 +105,7 @@ struct nv50_head_atom {
u8 depth:4; u8 depth:4;
} or; } or;
union { union nv50_head_atom_mask {
struct {
bool ilut:1;
bool core:1;
bool curs:1;
};
u8 mask;
} clr;
union {
struct { struct {
bool ilut:1; bool ilut:1;
bool core:1; bool core:1;
@@ -128,7 +119,7 @@ struct nv50_head_atom {
bool or:1; bool or:1;
}; };
u16 mask; u16 mask;
} set; } set, clr;
}; };
static inline struct nv50_head_atom * static inline struct nv50_head_atom *
@@ -184,16 +175,7 @@ struct nv50_wndw_atom {
u16 y; u16 y;
} point; } point;
union { union nv50_wndw_atom_mask {
struct {
bool ntfy:1;
bool sema:1;
bool image:1;
};
u8 mask;
} clr;
union {
struct { struct {
bool ntfy:1; bool ntfy:1;
bool sema:1; bool sema:1;
@@ -202,6 +184,6 @@ struct nv50_wndw_atom {
bool point:1; bool point:1;
}; };
u8 mask; u8 mask;
} set; } set, clr;
}; };
#endif #endif

11
drivers/gpu/drm/nouveau/dispnv50/disp.c
View File

@@ -62,19 +62,12 @@ struct nv50_outp_atom {
struct drm_encoder *encoder; struct drm_encoder *encoder;
bool flush_disable; bool flush_disable;
union { union nv50_outp_atom_mask {
struct { struct {
bool ctrl:1; bool ctrl:1;
}; };
u8 mask; u8 mask;
} clr; } set, clr;
union {
struct {
bool ctrl:1;
};
u8 mask;
} set;
}; };
/****************************************************************************** /******************************************************************************

15
drivers/gpu/drm/nouveau/dispnv50/head.c
View File

@@ -81,14 +81,15 @@ nv50_head_lut_load(struct drm_property_blob *blob, int mode,
} }
void void
nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y) nv50_head_flush_clr(struct nv50_head *head,
struct nv50_head_atom *asyh, bool flush)
{ {
if (asyh->clr.ilut && (!asyh->set.ilut || y)) union nv50_head_atom_mask clr = {
head->func->ilut_clr(head); .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
if (asyh->clr.core && (!asyh->set.core || y)) };
head->func->core_clr(head); if (clr.ilut) head->func->ilut_clr(head);
if (asyh->clr.curs && (!asyh->set.curs || y)) if (clr.core) head->func->core_clr(head);
head->func->curs_clr(head); if (clr.curs) head->func->curs_clr(head);
} }
void void

12
drivers/gpu/drm/nouveau/dispnv50/wndw.c
View File

@@ -111,12 +111,12 @@ u32
nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush, nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
struct nv50_wndw_atom *asyw) struct nv50_wndw_atom *asyw)
{ {
if (asyw->clr.sema && (!asyw->set.sema || flush)) union nv50_wndw_atom_mask clr = {
wndw->func->sema_clr(wndw); .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
if (asyw->clr.ntfy && (!asyw->set.ntfy || flush)) };
wndw->func->ntfy_clr(wndw); if (clr.sema ) wndw->func-> sema_clr(wndw);
if (asyw->clr.image && (!asyw->set.image || flush)) if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
wndw->func->image_clr(wndw); if (clr.image) wndw->func->image_clr(wndw);
return flush ? wndw->func->update(wndw, interlock) : 0; return flush ? wndw->func->update(wndw, interlock) : 0;
} }