clk: tegra: dfll: Properly clean up on failure and removal
Upon failure to probe the DFLL, the OPP table will not be cleaned up properly. Fix this and while at it make sure the OPP table will also be cleared upon driver removal. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@@ -25,6 +25,7 @@
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/**
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* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
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* @dev: struct device * that holds the OPP table for the DFLL
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* @max_freq: maximum frequency supported on this SoC
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* @cvb: CPU frequency table for this SoC
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* @init_clock_trimmers: callback to initialize clock trimmers
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* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
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@@ -32,6 +33,7 @@
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*/
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struct tegra_dfll_soc_data {
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struct device *dev;
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unsigned long max_freq;
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const struct cvb_table *cvb;
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void (*init_clock_trimmers)(void);
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