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drm/nouveau: Cleanup indenting in nouveau_backlight.c

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Still no functional changes.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Lyude Paul
2018-09-06 17:43:25 -04:00
committed by Ben Skeggs
parent a4e05f415e
commit f76e174bd3
1 changed files with 7 additions and 6 deletions
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13
drivers/gpu/drm/nouveau/nouveau_backlight.c
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@@ -68,7 +68,7 @@ nv40_get_intensity(struct backlight_device *bd)
struct nouveau_drm *drm = bl_get_data(bd); struct nouveau_drm *drm = bl_get_data(bd);
struct nvif_object *device = &drm->client.device.object; struct nvif_object *device = &drm->client.device.object;
int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) &
NV40_PMC_BACKLIGHT_MASK) >> 16; NV40_PMC_BACKLIGHT_MASK) >> 16;
return val; return val;
} }
@@ -82,7 +82,7 @@ nv40_set_intensity(struct backlight_device *bd)
int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT);
nvif_wr32(device, NV40_PMC_BACKLIGHT, nvif_wr32(device, NV40_PMC_BACKLIGHT,
(val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK)); (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK));
return 0; return 0;
} }
@@ -164,7 +164,7 @@ nv50_set_intensity(struct backlight_device *bd)
u32 val = (bd->props.brightness * div) / 100; u32 val = (bd->props.brightness * div) / 100;
nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or),
NV50_PDISP_SOR_PWM_CTL_NEW | val); NV50_PDISP_SOR_PWM_CTL_NEW | val);
return 0; return 0;
} }
@@ -204,9 +204,10 @@ nva3_set_intensity(struct backlight_device *bd)
div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or));
val = (bd->props.brightness * div) / 100; val = (bd->props.brightness * div) / 100;
if (div) { if (div) {
nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), val | nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or),
NV50_PDISP_SOR_PWM_CTL_NEW | val |
NVA3_PDISP_SOR_PWM_CTL_UNK); NV50_PDISP_SOR_PWM_CTL_NEW |
NVA3_PDISP_SOR_PWM_CTL_UNK);
return 0; return 0;
} }