i386: move kernel/cpu
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner
806
arch/x86/kernel/cpu/intel_cacheinfo.c
Normal file
806
arch/x86/kernel/cpu/intel_cacheinfo.c
Normal file
@@ -0,0 +1,806 @@
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/*
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* Routines to indentify caches on Intel CPU.
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*
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* Changes:
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* Venkatesh Pallipadi : Adding cache identification through cpuid(4)
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* Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
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* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/compiler.h>
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#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/smp.h>
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#define LVL_1_INST 1
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#define LVL_1_DATA 2
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#define LVL_2 3
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#define LVL_3 4
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#define LVL_TRACE 5
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struct _cache_table
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{
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unsigned char descriptor;
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char cache_type;
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short size;
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};
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/* all the cache descriptor types we care about (no TLB or trace cache entries) */
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static struct _cache_table cache_table[] __cpuinitdata =
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{
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{ 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
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{ 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
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{ 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
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{ 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
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{ 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x29, LVL_3, 4096 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
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{ 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
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{ 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
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{ 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
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{ 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
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{ 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
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{ 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
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{ 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
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{ 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
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{ 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
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{ 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
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{ 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
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{ 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
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{ 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
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{ 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
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{ 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
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{ 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
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{ 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
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{ 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
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{ 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
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{ 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
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{ 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
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{ 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7c, LVL_2, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7d, LVL_2, 2048 }, /* 8-way set assoc, 64 byte line size */
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{ 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
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{ 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
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{ 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
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{ 0x84, LVL_2, 1024 }, /* 8-way set assoc, 32 byte line size */
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{ 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */
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{ 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
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{ 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */
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{ 0x00, 0, 0}
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};
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enum _cache_type
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{
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CACHE_TYPE_NULL = 0,
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CACHE_TYPE_DATA = 1,
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CACHE_TYPE_INST = 2,
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CACHE_TYPE_UNIFIED = 3
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};
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union _cpuid4_leaf_eax {
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struct {
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enum _cache_type type:5;
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unsigned int level:3;
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unsigned int is_self_initializing:1;
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unsigned int is_fully_associative:1;
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unsigned int reserved:4;
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unsigned int num_threads_sharing:12;
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unsigned int num_cores_on_die:6;
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} split;
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u32 full;
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};
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union _cpuid4_leaf_ebx {
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struct {
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unsigned int coherency_line_size:12;
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unsigned int physical_line_partition:10;
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unsigned int ways_of_associativity:10;
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} split;
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u32 full;
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};
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union _cpuid4_leaf_ecx {
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struct {
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unsigned int number_of_sets:32;
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} split;
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u32 full;
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};
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struct _cpuid4_info {
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned long size;
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cpumask_t shared_cpu_map;
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};
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unsigned short num_cache_leaves;
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/* AMD doesn't have CPUID4. Emulate it here to report the same
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information to the user. This makes some assumptions about the machine:
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L2 not shared, no SMT etc. that is currently true on AMD CPUs.
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In theory the TLBs could be reported as fake type (they are in "dummy").
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Maybe later */
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union l1_cache {
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struct {
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unsigned line_size : 8;
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unsigned lines_per_tag : 8;
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unsigned assoc : 8;
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unsigned size_in_kb : 8;
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};
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unsigned val;
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};
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union l2_cache {
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struct {
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unsigned line_size : 8;
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unsigned lines_per_tag : 4;
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unsigned assoc : 4;
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unsigned size_in_kb : 16;
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};
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unsigned val;
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};
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union l3_cache {
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struct {
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unsigned line_size : 8;
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unsigned lines_per_tag : 4;
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unsigned assoc : 4;
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unsigned res : 2;
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unsigned size_encoded : 14;
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};
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unsigned val;
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};
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static const unsigned short assocs[] = {
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[1] = 1, [2] = 2, [4] = 4, [6] = 8,
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[8] = 16, [0xa] = 32, [0xb] = 48,
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[0xc] = 64,
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[0xf] = 0xffff // ??
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};
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static const unsigned char levels[] = { 1, 1, 2, 3 };
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static const unsigned char types[] = { 1, 2, 3, 3 };
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static void __cpuinit amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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union _cpuid4_leaf_ebx *ebx,
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union _cpuid4_leaf_ecx *ecx)
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{
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unsigned dummy;
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unsigned line_size, lines_per_tag, assoc, size_in_kb;
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union l1_cache l1i, l1d;
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union l2_cache l2;
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union l3_cache l3;
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union l1_cache *l1 = &l1d;
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eax->full = 0;
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ebx->full = 0;
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ecx->full = 0;
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cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
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cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
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switch (leaf) {
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case 1:
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l1 = &l1i;
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case 0:
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if (!l1->val)
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return;
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assoc = l1->assoc;
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line_size = l1->line_size;
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lines_per_tag = l1->lines_per_tag;
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size_in_kb = l1->size_in_kb;
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break;
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case 2:
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if (!l2.val)
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return;
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assoc = l2.assoc;
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line_size = l2.line_size;
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lines_per_tag = l2.lines_per_tag;
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/* cpu_data has errata corrections for K7 applied */
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size_in_kb = current_cpu_data.x86_cache_size;
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break;
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case 3:
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if (!l3.val)
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return;
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assoc = l3.assoc;
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line_size = l3.line_size;
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lines_per_tag = l3.lines_per_tag;
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size_in_kb = l3.size_encoded * 512;
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break;
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default:
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return;
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}
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eax->split.is_self_initializing = 1;
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eax->split.type = types[leaf];
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eax->split.level = levels[leaf];
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if (leaf == 3)
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eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
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else
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eax->split.num_threads_sharing = 0;
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eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
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if (assoc == 0xf)
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eax->split.is_fully_associative = 1;
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ebx->split.coherency_line_size = line_size - 1;
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ebx->split.ways_of_associativity = assocs[assoc] - 1;
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ebx->split.physical_line_partition = lines_per_tag - 1;
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ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
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(ebx->split.ways_of_associativity + 1) - 1;
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}
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static int __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
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{
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned edx;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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amd_cpuid4(index, &eax, &ebx, &ecx);
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else
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cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
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if (eax.split.type == CACHE_TYPE_NULL)
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return -EIO; /* better error ? */
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this_leaf->eax = eax;
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this_leaf->ebx = ebx;
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this_leaf->ecx = ecx;
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this_leaf->size = (ecx.split.number_of_sets + 1) *
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(ebx.split.coherency_line_size + 1) *
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(ebx.split.physical_line_partition + 1) *
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(ebx.split.ways_of_associativity + 1);
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return 0;
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}
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static int __cpuinit find_num_cache_leaves(void)
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{
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unsigned int eax, ebx, ecx, edx;
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union _cpuid4_leaf_eax cache_eax;
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int i = -1;
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do {
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++i;
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/* Do cpuid(4) loop to find out num_cache_leaves */
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cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
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cache_eax.full = eax;
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} while (cache_eax.split.type != CACHE_TYPE_NULL);
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return i;
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}
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unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
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unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
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unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
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unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
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#ifdef CONFIG_X86_HT
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unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data);
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#endif
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if (c->cpuid_level > 3) {
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static int is_initialized;
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if (is_initialized == 0) {
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/* Init num_cache_leaves from boot CPU */
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num_cache_leaves = find_num_cache_leaves();
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is_initialized++;
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}
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/*
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* Whenever possible use cpuid(4), deterministic cache
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* parameters cpuid leaf to find the cache details
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*/
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for (i = 0; i < num_cache_leaves; i++) {
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struct _cpuid4_info this_leaf;
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int retval;
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retval = cpuid4_cache_lookup(i, &this_leaf);
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if (retval >= 0) {
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switch(this_leaf.eax.split.level) {
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case 1:
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if (this_leaf.eax.split.type ==
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CACHE_TYPE_DATA)
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new_l1d = this_leaf.size/1024;
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else if (this_leaf.eax.split.type ==
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CACHE_TYPE_INST)
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new_l1i = this_leaf.size/1024;
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break;
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case 2:
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new_l2 = this_leaf.size/1024;
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num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
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index_msb = get_count_order(num_threads_sharing);
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l2_id = c->apicid >> index_msb;
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break;
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case 3:
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new_l3 = this_leaf.size/1024;
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num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
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index_msb = get_count_order(num_threads_sharing);
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l3_id = c->apicid >> index_msb;
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break;
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default:
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break;
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}
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}
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}
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}
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/*
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* Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
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* trace cache
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*/
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if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
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/* supports eax=2 call */
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int i, j, n;
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int regs[4];
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unsigned char *dp = (unsigned char *)regs;
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int only_trace = 0;
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if (num_cache_leaves != 0 && c->x86 == 15)
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only_trace = 1;
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/* Number of times to iterate */
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n = cpuid_eax(2) & 0xFF;
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for ( i = 0 ; i < n ; i++ ) {
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cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
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/* If bit 31 is set, this is an unknown format */
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for ( j = 0 ; j < 3 ; j++ ) {
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if ( regs[j] < 0 ) regs[j] = 0;
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}
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/* Byte 0 is level count, not a descriptor */
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for ( j = 1 ; j < 16 ; j++ ) {
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unsigned char des = dp[j];
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unsigned char k = 0;
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/* look up this descriptor in the table */
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while (cache_table[k].descriptor != 0)
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{
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if (cache_table[k].descriptor == des) {
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if (only_trace && cache_table[k].cache_type != LVL_TRACE)
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break;
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switch (cache_table[k].cache_type) {
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case LVL_1_INST:
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l1i += cache_table[k].size;
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break;
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case LVL_1_DATA:
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l1d += cache_table[k].size;
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break;
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case LVL_2:
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l2 += cache_table[k].size;
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break;
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case LVL_3:
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l3 += cache_table[k].size;
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break;
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case LVL_TRACE:
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trace += cache_table[k].size;
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break;
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}
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break;
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}
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k++;
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}
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}
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}
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}
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if (new_l1d)
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l1d = new_l1d;
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if (new_l1i)
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l1i = new_l1i;
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if (new_l2) {
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l2 = new_l2;
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#ifdef CONFIG_X86_HT
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cpu_llc_id[cpu] = l2_id;
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#endif
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}
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if (new_l3) {
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l3 = new_l3;
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||||
#ifdef CONFIG_X86_HT
|
||||
cpu_llc_id[cpu] = l3_id;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (trace)
|
||||
printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
|
||||
else if ( l1i )
|
||||
printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
|
||||
|
||||
if (l1d)
|
||||
printk(", L1 D cache: %dK\n", l1d);
|
||||
else
|
||||
printk("\n");
|
||||
|
||||
if (l2)
|
||||
printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
|
||||
|
||||
if (l3)
|
||||
printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
|
||||
|
||||
c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
|
||||
|
||||
return l2;
|
||||
}
|
||||
|
||||
/* pointer to _cpuid4_info array (for each cache leaf) */
|
||||
static struct _cpuid4_info *cpuid4_info[NR_CPUS];
|
||||
#define CPUID4_INFO_IDX(x,y) (&((cpuid4_info[x])[y]))
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
|
||||
{
|
||||
struct _cpuid4_info *this_leaf, *sibling_leaf;
|
||||
unsigned long num_threads_sharing;
|
||||
int index_msb, i;
|
||||
struct cpuinfo_x86 *c = cpu_data;
|
||||
|
||||
this_leaf = CPUID4_INFO_IDX(cpu, index);
|
||||
num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
|
||||
|
||||
if (num_threads_sharing == 1)
|
||||
cpu_set(cpu, this_leaf->shared_cpu_map);
|
||||
else {
|
||||
index_msb = get_count_order(num_threads_sharing);
|
||||
|
||||
for_each_online_cpu(i) {
|
||||
if (c[i].apicid >> index_msb ==
|
||||
c[cpu].apicid >> index_msb) {
|
||||
cpu_set(i, this_leaf->shared_cpu_map);
|
||||
if (i != cpu && cpuid4_info[i]) {
|
||||
sibling_leaf = CPUID4_INFO_IDX(i, index);
|
||||
cpu_set(cpu, sibling_leaf->shared_cpu_map);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
|
||||
{
|
||||
struct _cpuid4_info *this_leaf, *sibling_leaf;
|
||||
int sibling;
|
||||
|
||||
this_leaf = CPUID4_INFO_IDX(cpu, index);
|
||||
for_each_cpu_mask(sibling, this_leaf->shared_cpu_map) {
|
||||
sibling_leaf = CPUID4_INFO_IDX(sibling, index);
|
||||
cpu_clear(cpu, sibling_leaf->shared_cpu_map);
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void __init cache_shared_cpu_map_setup(unsigned int cpu, int index) {}
|
||||
static void __init cache_remove_shared_cpu_map(unsigned int cpu, int index) {}
|
||||
#endif
|
||||
|
||||
static void free_cache_attributes(unsigned int cpu)
|
||||
{
|
||||
kfree(cpuid4_info[cpu]);
|
||||
cpuid4_info[cpu] = NULL;
|
||||
}
|
||||
|
||||
static int __cpuinit detect_cache_attributes(unsigned int cpu)
|
||||
{
|
||||
struct _cpuid4_info *this_leaf;
|
||||
unsigned long j;
|
||||
int retval;
|
||||
cpumask_t oldmask;
|
||||
|
||||
if (num_cache_leaves == 0)
|
||||
return -ENOENT;
|
||||
|
||||
cpuid4_info[cpu] = kzalloc(
|
||||
sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
|
||||
if (cpuid4_info[cpu] == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
oldmask = current->cpus_allowed;
|
||||
retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
|
||||
if (retval)
|
||||
goto out;
|
||||
|
||||
/* Do cpuid and store the results */
|
||||
retval = 0;
|
||||
for (j = 0; j < num_cache_leaves; j++) {
|
||||
this_leaf = CPUID4_INFO_IDX(cpu, j);
|
||||
retval = cpuid4_cache_lookup(j, this_leaf);
|
||||
if (unlikely(retval < 0))
|
||||
break;
|
||||
cache_shared_cpu_map_setup(cpu, j);
|
||||
}
|
||||
set_cpus_allowed(current, oldmask);
|
||||
|
||||
out:
|
||||
if (retval)
|
||||
free_cache_attributes(cpu);
|
||||
return retval;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYSFS
|
||||
|
||||
#include <linux/kobject.h>
|
||||
#include <linux/sysfs.h>
|
||||
|
||||
extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
|
||||
|
||||
/* pointer to kobject for cpuX/cache */
|
||||
static struct kobject * cache_kobject[NR_CPUS];
|
||||
|
||||
struct _index_kobject {
|
||||
struct kobject kobj;
|
||||
unsigned int cpu;
|
||||
unsigned short index;
|
||||
};
|
||||
|
||||
/* pointer to array of kobjects for cpuX/cache/indexY */
|
||||
static struct _index_kobject *index_kobject[NR_CPUS];
|
||||
#define INDEX_KOBJECT_PTR(x,y) (&((index_kobject[x])[y]))
|
||||
|
||||
#define show_one_plus(file_name, object, val) \
|
||||
static ssize_t show_##file_name \
|
||||
(struct _cpuid4_info *this_leaf, char *buf) \
|
||||
{ \
|
||||
return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
|
||||
}
|
||||
|
||||
show_one_plus(level, eax.split.level, 0);
|
||||
show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
|
||||
show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
|
||||
show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
|
||||
show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
|
||||
|
||||
static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
|
||||
{
|
||||
return sprintf (buf, "%luK\n", this_leaf->size / 1024);
|
||||
}
|
||||
|
||||
static ssize_t show_shared_cpu_map(struct _cpuid4_info *this_leaf, char *buf)
|
||||
{
|
||||
char mask_str[NR_CPUS];
|
||||
cpumask_scnprintf(mask_str, NR_CPUS, this_leaf->shared_cpu_map);
|
||||
return sprintf(buf, "%s\n", mask_str);
|
||||
}
|
||||
|
||||
static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
|
||||
switch(this_leaf->eax.split.type) {
|
||||
case CACHE_TYPE_DATA:
|
||||
return sprintf(buf, "Data\n");
|
||||
break;
|
||||
case CACHE_TYPE_INST:
|
||||
return sprintf(buf, "Instruction\n");
|
||||
break;
|
||||
case CACHE_TYPE_UNIFIED:
|
||||
return sprintf(buf, "Unified\n");
|
||||
break;
|
||||
default:
|
||||
return sprintf(buf, "Unknown\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
struct _cache_attr {
|
||||
struct attribute attr;
|
||||
ssize_t (*show)(struct _cpuid4_info *, char *);
|
||||
ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
|
||||
};
|
||||
|
||||
#define define_one_ro(_name) \
|
||||
static struct _cache_attr _name = \
|
||||
__ATTR(_name, 0444, show_##_name, NULL)
|
||||
|
||||
define_one_ro(level);
|
||||
define_one_ro(type);
|
||||
define_one_ro(coherency_line_size);
|
||||
define_one_ro(physical_line_partition);
|
||||
define_one_ro(ways_of_associativity);
|
||||
define_one_ro(number_of_sets);
|
||||
define_one_ro(size);
|
||||
define_one_ro(shared_cpu_map);
|
||||
|
||||
static struct attribute * default_attrs[] = {
|
||||
&type.attr,
|
||||
&level.attr,
|
||||
&coherency_line_size.attr,
|
||||
&physical_line_partition.attr,
|
||||
&ways_of_associativity.attr,
|
||||
&number_of_sets.attr,
|
||||
&size.attr,
|
||||
&shared_cpu_map.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
#define to_object(k) container_of(k, struct _index_kobject, kobj)
|
||||
#define to_attr(a) container_of(a, struct _cache_attr, attr)
|
||||
|
||||
static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
|
||||
{
|
||||
struct _cache_attr *fattr = to_attr(attr);
|
||||
struct _index_kobject *this_leaf = to_object(kobj);
|
||||
ssize_t ret;
|
||||
|
||||
ret = fattr->show ?
|
||||
fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
|
||||
buf) :
|
||||
0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t store(struct kobject * kobj, struct attribute * attr,
|
||||
const char * buf, size_t count)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysfs_ops sysfs_ops = {
|
||||
.show = show,
|
||||
.store = store,
|
||||
};
|
||||
|
||||
static struct kobj_type ktype_cache = {
|
||||
.sysfs_ops = &sysfs_ops,
|
||||
.default_attrs = default_attrs,
|
||||
};
|
||||
|
||||
static struct kobj_type ktype_percpu_entry = {
|
||||
.sysfs_ops = &sysfs_ops,
|
||||
};
|
||||
|
||||
static void cpuid4_cache_sysfs_exit(unsigned int cpu)
|
||||
{
|
||||
kfree(cache_kobject[cpu]);
|
||||
kfree(index_kobject[cpu]);
|
||||
cache_kobject[cpu] = NULL;
|
||||
index_kobject[cpu] = NULL;
|
||||
free_cache_attributes(cpu);
|
||||
}
|
||||
|
||||
static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
|
||||
{
|
||||
|
||||
if (num_cache_leaves == 0)
|
||||
return -ENOENT;
|
||||
|
||||
detect_cache_attributes(cpu);
|
||||
if (cpuid4_info[cpu] == NULL)
|
||||
return -ENOENT;
|
||||
|
||||
/* Allocate all required memory */
|
||||
cache_kobject[cpu] = kzalloc(sizeof(struct kobject), GFP_KERNEL);
|
||||
if (unlikely(cache_kobject[cpu] == NULL))
|
||||
goto err_out;
|
||||
|
||||
index_kobject[cpu] = kzalloc(
|
||||
sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
|
||||
if (unlikely(index_kobject[cpu] == NULL))
|
||||
goto err_out;
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
cpuid4_cache_sysfs_exit(cpu);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Add/Remove cache interface for CPU device */
|
||||
static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
|
||||
{
|
||||
unsigned int cpu = sys_dev->id;
|
||||
unsigned long i, j;
|
||||
struct _index_kobject *this_object;
|
||||
int retval = 0;
|
||||
|
||||
retval = cpuid4_cache_sysfs_init(cpu);
|
||||
if (unlikely(retval < 0))
|
||||
return retval;
|
||||
|
||||
cache_kobject[cpu]->parent = &sys_dev->kobj;
|
||||
kobject_set_name(cache_kobject[cpu], "%s", "cache");
|
||||
cache_kobject[cpu]->ktype = &ktype_percpu_entry;
|
||||
retval = kobject_register(cache_kobject[cpu]);
|
||||
|
||||
for (i = 0; i < num_cache_leaves; i++) {
|
||||
this_object = INDEX_KOBJECT_PTR(cpu,i);
|
||||
this_object->cpu = cpu;
|
||||
this_object->index = i;
|
||||
this_object->kobj.parent = cache_kobject[cpu];
|
||||
kobject_set_name(&(this_object->kobj), "index%1lu", i);
|
||||
this_object->kobj.ktype = &ktype_cache;
|
||||
retval = kobject_register(&(this_object->kobj));
|
||||
if (unlikely(retval)) {
|
||||
for (j = 0; j < i; j++) {
|
||||
kobject_unregister(
|
||||
&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
|
||||
}
|
||||
kobject_unregister(cache_kobject[cpu]);
|
||||
cpuid4_cache_sysfs_exit(cpu);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
|
||||
{
|
||||
unsigned int cpu = sys_dev->id;
|
||||
unsigned long i;
|
||||
|
||||
if (cpuid4_info[cpu] == NULL)
|
||||
return;
|
||||
for (i = 0; i < num_cache_leaves; i++) {
|
||||
cache_remove_shared_cpu_map(cpu, i);
|
||||
kobject_unregister(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
|
||||
}
|
||||
kobject_unregister(cache_kobject[cpu]);
|
||||
cpuid4_cache_sysfs_exit(cpu);
|
||||
return;
|
||||
}
|
||||
|
||||
static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
unsigned int cpu = (unsigned long)hcpu;
|
||||
struct sys_device *sys_dev;
|
||||
|
||||
sys_dev = get_cpu_sysdev(cpu);
|
||||
switch (action) {
|
||||
case CPU_ONLINE:
|
||||
case CPU_ONLINE_FROZEN:
|
||||
cache_add_dev(sys_dev);
|
||||
break;
|
||||
case CPU_DEAD:
|
||||
case CPU_DEAD_FROZEN:
|
||||
cache_remove_dev(sys_dev);
|
||||
break;
|
||||
}
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier =
|
||||
{
|
||||
.notifier_call = cacheinfo_cpu_callback,
|
||||
};
|
||||
|
||||
static int __cpuinit cache_sysfs_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (num_cache_leaves == 0)
|
||||
return 0;
|
||||
|
||||
register_hotcpu_notifier(&cacheinfo_cpu_notifier);
|
||||
|
||||
for_each_online_cpu(i) {
|
||||
cacheinfo_cpu_callback(&cacheinfo_cpu_notifier, CPU_ONLINE,
|
||||
(void *)(long)i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(cache_sysfs_init);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user