drm/i915/glk: Update Port PLL enable sequence for Geminilkae
Add steps for enabling and disabling Port PLL as per bspec. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-6-git-send-email-ander.conselvan.de.oliveira@intel.com
This commit is contained in:

committed by
Ander Conselvan de Oliveira

parent
51b3ee35af
commit
f7044dd904
@@ -1574,6 +1574,8 @@ enum skl_disp_power_wells {
|
||||
#define PORT_PLL_ENABLE (1 << 31)
|
||||
#define PORT_PLL_LOCK (1 << 30)
|
||||
#define PORT_PLL_REF_SEL (1 << 27)
|
||||
#define PORT_PLL_POWER_ENABLE (1 << 26)
|
||||
#define PORT_PLL_POWER_STATE (1 << 25)
|
||||
#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
|
||||
|
||||
#define _PORT_PLL_EBB_0_A 0x162034
|
||||
|
Reference in New Issue
Block a user