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MIPS: math-emu: Set FIR feature flags for full emulation

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Implement FIR feature flags in the FPU emulator according to features
supported and architecture level requirements.  The W, L and F64 bits
have only been added at level #2 even though the features they refer to
were also included with the MIPS64r1 ISA and the W fixed-point format
also with the MIPS32r1 ISA.

This is only relevant for the full emulation mode and the emulated CFC1
instruction as well as ptrace(2) accesses.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
2015-04-03 23:27:26 +01:00
committed by Ralf Baechle
parent 9cb60e2026
commit f684362689
2 changed files with 25 additions and 3 deletions
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3
arch/mips/math-emu/cp1emu.c
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@@ -45,6 +45,7 @@
#include <asm/signal.h>
#include <asm/uaccess.h>
#include <asm/cpu-info.h>
#include <asm/processor.h>
#include <asm/fpu_emulator.h>
#include <asm/fpu.h>
@@ -853,7 +854,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
(void *)xcp->cp0_epc,
MIPSInst_RT(ir), value);
} else if (MIPSInst_RD(ir) == FPCREG_RID)
value = 0;
value = current_cpu_data.fpu_id;
else
value = 0;
if (MIPSInst_RT(ir))