Merge tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "The majority of the changes are driver updates and new device support. The core framework is mostly unchanged this time around, with only a couple patches to expose a clk provider API and make getting clk parent names from DT more robust. Driver updates: - Support for clock controllers found on Broadcom Northstar SoCs and bcm2835 SoC - Support for Allwinner audio clocks - A few cleanup patches for Tegra drivers and support for the highest DFLL frequencies on Tegra124 - Samsung exynos7 fixes and improvements - i.Mx SoC updates to add a few missing clocks and keep debug uart clocks on during kernel intialization - Some mediatek cleanups and support for more subsystem clocks - Support for msm8916 gpu/audio clocks and qcom's GDSC power domain controllers - A new driver for the Silabs si514 clock chip" * tag 'clk-for-linus-20151104' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (143 commits) clk: qcom: msm8960: Fix dsi1/2 halt bits clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks clk: Add clk_hw_is_enabled() for use by clk providers clk: Add stubs for of_clk_*() APIs when CONFIG_OF=n clk: versatile-icst: fix memory leak clk: Remove clk_{register,unregister}_multiplier() clk: iproc: define Broadcom NS2 iProc clock binding clk: iproc: define Broadcom NSP iProc clock binding clk: ns2: add clock support for Broadcom Northstar 2 SoC clk: iproc: Separate status and control variables clk: iproc: Split off dig_filter clk: iproc: Add PLL base write function clk: nsp: add clock support for Broadcom Northstar Plus SoC clk: iproc: Add PWRCTRL support clk: cygnus: Convert all macros to all caps ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabled clk: imx31: add missing of_node_put clk: imx27: add missing of_node_put clk: si5351: add missing of_node_put ...
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@@ -41,6 +41,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
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#define ROCKCHIP_MMC_DEGREE_MASK 0x3
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#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
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#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
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#define ROCKCHIP_MMC_INIT_STATE_RESET 0x1
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#define ROCKCHIP_MMC_INIT_STATE_SHIFT 1
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#define PSECS_PER_SEC 1000000000000LL
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@@ -159,6 +161,15 @@ struct clk *rockchip_clk_register_mmc(const char *name,
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mmc_clock->reg = reg;
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mmc_clock->shift = shift;
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/*
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* Assert init_state to soft reset the CLKGEN
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* for mmc tuning phase and degree
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*/
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if (mmc_clock->shift == ROCKCHIP_MMC_INIT_STATE_SHIFT)
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writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET,
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ROCKCHIP_MMC_INIT_STATE_RESET,
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mmc_clock->shift), mmc_clock->reg);
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clk = clk_register(NULL, &mmc_clock->hw);
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if (IS_ERR(clk))
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goto err_free;
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