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iio: adc: stx104: Implement and utilize register structures

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[ Upstream commit 6cfd14c54b1f42f29097244c1b6208f8268d7d5b ]

Reduce magic numbers and improve code readability by implementing and
utilizing named register data structures.

Tested-by: Fred Eckert <Frede@cmslaser.com>
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Link: https://lore.kernel.org/r/8cb91d5b53e57b066120e42ea07000d6c7ef5543.1657213745.git.william.gray@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
William Breathitt Gray
2022-07-07 13:21:24 -04:00
committed by Greg Kroah-Hartman
parent 9d16098245
commit f6576d4851
1 changed files with 50 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
drivers/iio/adc/stx104.c
View File

@@ -16,6 +16,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/moduleparam.h> #include <linux/moduleparam.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/types.h>
#define STX104_OUT_CHAN(chan) { \ #define STX104_OUT_CHAN(chan) { \
.type = IIO_VOLTAGE, \ .type = IIO_VOLTAGE, \
@@ -44,14 +45,36 @@ static unsigned int num_stx104;
module_param_hw_array(base, uint, ioport, &num_stx104, 0); module_param_hw_array(base, uint, ioport, &num_stx104, 0);
MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses");
/**
* struct stx104_reg - device register structure
* @ssr_ad: Software Strobe Register and ADC Data
* @achan: ADC Channel
* @dio: Digital I/O
* @dac: DAC Channels
* @cir_asr: Clear Interrupts and ADC Status
* @acr: ADC Control
* @pccr_fsh: Pacer Clock Control and FIFO Status MSB
* @acfg: ADC Configuration
*/
struct stx104_reg {
u16 ssr_ad;
u8 achan;
u8 dio;
u16 dac[2];
u8 cir_asr;
u8 acr;
u8 pccr_fsh;
u8 acfg;
};
/** /**
* struct stx104_iio - IIO device private data structure * struct stx104_iio - IIO device private data structure
* @chan_out_states: channels' output states * @chan_out_states: channels' output states
* @base: base port address of the IIO device * @reg: I/O address offset for the device registers
*/ */
struct stx104_iio { struct stx104_iio {
unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; unsigned int chan_out_states[STX104_NUM_OUT_CHAN];
void __iomem *base; struct stx104_reg __iomem *reg;
}; };
/** /**
@@ -64,7 +87,7 @@ struct stx104_iio {
struct stx104_gpio { struct stx104_gpio {
struct gpio_chip chip; struct gpio_chip chip;
spinlock_t lock; spinlock_t lock;
void __iomem *base; u8 __iomem *base;
unsigned int out_state; unsigned int out_state;
}; };
@@ -72,6 +95,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long mask) struct iio_chan_spec const *chan, int *val, int *val2, long mask)
{ {
struct stx104_iio *const priv = iio_priv(indio_dev); struct stx104_iio *const priv = iio_priv(indio_dev);
struct stx104_reg __iomem *const reg = priv->reg;
unsigned int adc_config; unsigned int adc_config;
int adbu; int adbu;
int gain; int gain;
@@ -79,7 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
switch (mask) { switch (mask) {
case IIO_CHAN_INFO_HARDWAREGAIN: case IIO_CHAN_INFO_HARDWAREGAIN:
/* get gain configuration */ /* get gain configuration */
adc_config = ioread8(priv->base + 11); adc_config = ioread8(&reg->acfg);
gain = adc_config & 0x3; gain = adc_config & 0x3;
*val = 1 << gain; *val = 1 << gain;
@@ -91,24 +115,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev,
} }
/* select ADC channel */ /* select ADC channel */
iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); iowrite8(chan->channel | (chan->channel << 4), &reg->achan);
/* trigger ADC sample capture and wait for completion */ /* trigger ADC sample capture by writing to the 8-bit
iowrite8(0, priv->base); * Software Strobe Register and wait for completion
while (ioread8(priv->base + 8) & BIT(7)); */
iowrite8(0, &reg->ssr_ad);
while (ioread8(&reg->cir_asr) & BIT(7));
*val = ioread16(priv->base); *val = ioread16(&reg->ssr_ad);
return IIO_VAL_INT; return IIO_VAL_INT;
case IIO_CHAN_INFO_OFFSET: case IIO_CHAN_INFO_OFFSET:
/* get ADC bipolar/unipolar configuration */ /* get ADC bipolar/unipolar configuration */
adc_config = ioread8(priv->base + 11); adc_config = ioread8(&reg->acfg);
adbu = !(adc_config & BIT(2)); adbu = !(adc_config & BIT(2));
*val = -32768 * adbu; *val = -32768 * adbu;
return IIO_VAL_INT; return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE: case IIO_CHAN_INFO_SCALE:
/* get ADC bipolar/unipolar and gain configuration */ /* get ADC bipolar/unipolar and gain configuration */
adc_config = ioread8(priv->base + 11); adc_config = ioread8(&reg->acfg);
adbu = !(adc_config & BIT(2)); adbu = !(adc_config & BIT(2));
gain = adc_config & 0x3; gain = adc_config & 0x3;
@@ -130,16 +156,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
/* Only four gain states (x1, x2, x4, x8) */ /* Only four gain states (x1, x2, x4, x8) */
switch (val) { switch (val) {
case 1: case 1:
iowrite8(0, priv->base + 11); iowrite8(0, &priv->reg->acfg);
break; break;
case 2: case 2:
iowrite8(1, priv->base + 11); iowrite8(1, &priv->reg->acfg);
break; break;
case 4: case 4:
iowrite8(2, priv->base + 11); iowrite8(2, &priv->reg->acfg);
break; break;
case 8: case 8:
iowrite8(3, priv->base + 11); iowrite8(3, &priv->reg->acfg);
break; break;
default: default:
return -EINVAL; return -EINVAL;
@@ -153,7 +179,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
return -EINVAL; return -EINVAL;
priv->chan_out_states[chan->channel] = val; priv->chan_out_states[chan->channel] = val;
iowrite16(val, priv->base + 4 + 2 * chan->channel); iowrite16(val, &priv->reg->dac[chan->channel]);
return 0; return 0;
} }
@@ -307,15 +333,15 @@ static int stx104_probe(struct device *dev, unsigned int id)
} }
priv = iio_priv(indio_dev); priv = iio_priv(indio_dev);
priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT); priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT);
if (!priv->base) if (!priv->reg)
return -ENOMEM; return -ENOMEM;
indio_dev->info = &stx104_info; indio_dev->info = &stx104_info;
indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->modes = INDIO_DIRECT_MODE;
/* determine if differential inputs */ /* determine if differential inputs */
if (ioread8(priv->base + 8) & BIT(5)) { if (ioread8(&priv->reg->cir_asr) & BIT(5)) {
indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff);
indio_dev->channels = stx104_channels_diff; indio_dev->channels = stx104_channels_diff;
} else { } else {
@@ -326,14 +352,14 @@ static int stx104_probe(struct device *dev, unsigned int id)
indio_dev->name = dev_name(dev); indio_dev->name = dev_name(dev);
/* configure device for software trigger operation */ /* configure device for software trigger operation */
iowrite8(0, priv->base + 9); iowrite8(0, &priv->reg->acr);
/* initialize gain setting to x1 */ /* initialize gain setting to x1 */
iowrite8(0, priv->base + 11); iowrite8(0, &priv->reg->acfg);
/* initialize DAC output to 0V */ /* initialize DAC output to 0V */
iowrite16(0, priv->base + 4); iowrite16(0, &priv->reg->dac[0]);
iowrite16(0, priv->base + 6); iowrite16(0, &priv->reg->dac[1]);
stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.label = dev_name(dev);
stx104gpio->chip.parent = dev; stx104gpio->chip.parent = dev;
@@ -348,7 +374,7 @@ static int stx104_probe(struct device *dev, unsigned int id)
stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.get_multiple = stx104_gpio_get_multiple;
stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set = stx104_gpio_set;
stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple;
stx104gpio->base = priv->base + 3; stx104gpio->base = &priv->reg->dio;
stx104gpio->out_state = 0x0; stx104gpio->out_state = 0x0;
spin_lock_init(&stx104gpio->lock); spin_lock_init(&stx104gpio->lock);