xtensa: add SMP support
This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Max Filippov
committed by
Chris Zankel
Chris Zankel
parent
26a8e96a8b
commit
f615136c06
@@ -19,6 +19,7 @@
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#include <asm/page.h>
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#include <asm/cacheasm.h>
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#include <asm/initialize_mmu.h>
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#include <asm/mxregs.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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@@ -54,7 +55,7 @@ ENTRY(_start)
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/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
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wsr a2, excsave1
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_j _SetupMMU
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_j _SetupOCD
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.align 4
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.literal_position
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@@ -62,6 +63,23 @@ ENTRY(_start)
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.word _startup
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.align 4
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_SetupOCD:
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/*
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* Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
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* Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
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* xt-gdb to single step via DEBUG exceptions received directly
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* by ocd.
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*/
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movi a1, 1
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movi a0, 0
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wsr a1, windowstart
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wsr a0, windowbase
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rsync
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movi a1, LOCKLEVEL
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wsr a1, ps
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rsync
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.global _SetupMMU
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_SetupMMU:
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Offset = _SetupMMU - _start
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@@ -90,19 +108,6 @@ ENDPROC(_start)
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ENTRY(_startup)
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/* Disable interrupts and exceptions. */
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movi a0, LOCKLEVEL
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wsr a0, ps
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/* Start with a fresh windowbase and windowstart. */
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movi a1, 1
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movi a0, 0
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wsr a1, windowstart
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wsr a0, windowbase
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rsync
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/* Set a0 to 0 for the remaining initialization. */
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movi a0, 0
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@@ -154,17 +159,6 @@ ENTRY(_startup)
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wsr a0, cpenable
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#endif
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/* Set PS.INTLEVEL=LOCKLEVEL, PS.WOE=0, kernel stack, PS.EXCM=0
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*
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* Note: PS.EXCM must be cleared before using any loop
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* instructions; otherwise, they are silently disabled, and
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* at most one iteration of the loop is executed.
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*/
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movi a1, LOCKLEVEL
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wsr a1, ps
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rsync
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/* Initialize the caches.
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* a2, a3 are just working registers (clobbered).
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*/
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@@ -182,6 +176,37 @@ ENTRY(_startup)
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isync
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#ifdef CONFIG_HAVE_SMP
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movi a2, CCON # MX External Register to Configure Cache
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movi a3, 1
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wer a3, a2
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#endif
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/* Setup stack and enable window exceptions (keep irqs disabled) */
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movi a1, start_info
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l32i a1, a1, 0
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movi a2, (1 << PS_WOE_BIT) | LOCKLEVEL
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# WOE=1, INTLEVEL=LOCKLEVEL, UM=0
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wsr a2, ps # (enable reg-windows; progmode stack)
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rsync
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/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
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movi a2, debug_exception
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wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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#ifdef CONFIG_SMP
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/*
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* Notice that we assume with SMP that cores have PRID
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* supported by the cores.
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*/
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rsr a2, prid
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bnez a2, .Lboot_secondary
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#endif /* CONFIG_SMP */
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/* Unpack data sections
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*
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* The linker script used to build the Linux kernel image
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@@ -234,24 +259,7 @@ ENTRY(_startup)
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___invalidate_icache_all a2 a3
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isync
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/* Setup stack and enable window exceptions (keep irqs disabled) */
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movi a1, init_thread_union
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addi a1, a1, KERNEL_STACK_SIZE
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movi a2, (1 << PS_WOE_BIT) | LOCKLEVEL
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# WOE=1, INTLEVEL=LOCKLEVEL, UM=0
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wsr a2, ps # (enable reg-windows; progmode stack)
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rsync
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/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
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movi a2, debug_exception
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wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
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/* Set up EXCSAVE[1] to point to the exc_table. */
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movi a6, exc_table
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movi a6, 0
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xsr a6, excsave1
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/* init_arch kick-starts the linux kernel */
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@@ -265,8 +273,44 @@ ENTRY(_startup)
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should_never_return:
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j should_never_return
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#ifdef CONFIG_SMP
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.Lboot_secondary:
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movi a2, cpu_start_ccount
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1:
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l32i a3, a2, 0
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beqi a3, 0, 1b
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movi a3, 0
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s32i a3, a2, 0
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memw
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1:
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l32i a3, a2, 0
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beqi a3, 0, 1b
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wsr a3, ccount
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movi a3, 0
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s32i a3, a2, 0
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memw
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movi a6, 0
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wsr a6, excsave1
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movi a4, secondary_start_kernel
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callx4 a4
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j should_never_return
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#endif /* CONFIG_SMP */
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ENDPROC(_startup)
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/*
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* DATA section
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*/
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.section ".data.init.refok"
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.align 4
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ENTRY(start_info)
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.long init_thread_union + KERNEL_STACK_SIZE
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/*
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* BSS section
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*/
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