Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ...
This commit is contained in:
Linus Torvalds
@@ -5,3 +5,13 @@ config TEGRA_MC
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help
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This driver supports the Memory Controller (MC) hardware found on
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NVIDIA Tegra SoCs.
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config TEGRA124_EMC
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bool "NVIDIA Tegra124 External Memory Controller driver"
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default y
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depends on TEGRA_MC && ARCH_TEGRA_124_SOC
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help
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This driver is for the External Memory Controller (EMC) found on
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Tegra124 chips. The EMC controls the external DRAM on the board.
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This driver is required to change memory timings / clock rate for
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external memory.
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@@ -3,5 +3,8 @@ tegra-mc-y := mc.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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@@ -13,6 +13,9 @@
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/sort.h>
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#include <soc/tegra/fuse.h>
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#include "mc.h"
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@@ -48,6 +51,9 @@
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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static const struct of_device_id tegra_mc_of_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
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@@ -57,6 +63,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
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#endif
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{ }
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};
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@@ -91,6 +100,130 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
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return 0;
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}
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void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
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{
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unsigned int i;
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struct tegra_mc_timing *timing = NULL;
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for (i = 0; i < mc->num_timings; i++) {
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if (mc->timings[i].rate == rate) {
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timing = &mc->timings[i];
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break;
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}
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}
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if (!timing) {
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dev_err(mc->dev, "no memory timing registered for rate %lu\n",
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rate);
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return;
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}
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for (i = 0; i < mc->soc->num_emem_regs; ++i)
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mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
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}
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unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
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{
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u8 dram_count;
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dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
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dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
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dram_count++;
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return dram_count;
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}
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static int load_one_timing(struct tegra_mc *mc,
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struct tegra_mc_timing *timing,
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struct device_node *node)
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{
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int err;
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u32 tmp;
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err = of_property_read_u32(node, "clock-frequency", &tmp);
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if (err) {
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dev_err(mc->dev,
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"timing %s: failed to read rate\n", node->name);
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return err;
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}
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timing->rate = tmp;
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timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
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sizeof(u32), GFP_KERNEL);
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if (!timing->emem_data)
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return -ENOMEM;
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err = of_property_read_u32_array(node, "nvidia,emem-configuration",
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timing->emem_data,
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mc->soc->num_emem_regs);
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if (err) {
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dev_err(mc->dev,
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"timing %s: failed to read EMEM configuration\n",
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node->name);
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return err;
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}
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return 0;
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}
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static int load_timings(struct tegra_mc *mc, struct device_node *node)
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{
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struct device_node *child;
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struct tegra_mc_timing *timing;
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int child_count = of_get_child_count(node);
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int i = 0, err;
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mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
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GFP_KERNEL);
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if (!mc->timings)
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return -ENOMEM;
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mc->num_timings = child_count;
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for_each_child_of_node(node, child) {
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timing = &mc->timings[i++];
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err = load_one_timing(mc, timing, child);
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if (err)
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return err;
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}
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return 0;
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}
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static int tegra_mc_setup_timings(struct tegra_mc *mc)
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{
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struct device_node *node;
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u32 ram_code, node_ram_code;
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int err;
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ram_code = tegra_read_ram_code();
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mc->num_timings = 0;
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for_each_child_of_node(mc->dev->of_node, node) {
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err = of_property_read_u32(node, "nvidia,ram-code",
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&node_ram_code);
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if (err || (node_ram_code != ram_code)) {
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of_node_put(node);
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continue;
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}
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err = load_timings(mc, node);
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if (err)
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return err;
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of_node_put(node);
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break;
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}
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if (mc->num_timings == 0)
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dev_warn(mc->dev,
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"no memory timings for RAM code %u registered\n",
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ram_code);
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return 0;
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}
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static const char *const status_names[32] = {
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[ 1] = "External interrupt",
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[ 6] = "EMEM address decode error",
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@@ -248,6 +381,12 @@ static int tegra_mc_probe(struct platform_device *pdev)
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return err;
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}
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err = tegra_mc_setup_timings(mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
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return err;
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}
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if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
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mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
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if (IS_ERR(mc->smmu)) {
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@@ -273,8 +412,8 @@ static int tegra_mc_probe(struct platform_device *pdev)
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value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
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MC_INT_ARBITRATION_EMEM | MC_INT_SECURITY_VIOLATION |
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MC_INT_DECERR_EMEM;
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MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
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mc_writel(mc, value, MC_INTMASK);
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return 0;
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@@ -37,4 +37,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc;
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extern const struct tegra_mc_soc tegra124_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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extern const struct tegra_mc_soc tegra132_mc_soc;
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#endif
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#endif /* MEMORY_TEGRA_MC_H */
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@@ -896,22 +896,22 @@ static const struct tegra_mc_client tegra114_mc_clients[] = {
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};
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static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
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{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
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{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
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{ .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
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{ .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
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{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
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{ .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
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{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
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{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
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{ .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
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{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
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{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
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{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
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{ .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
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{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
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{ .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
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{ .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
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{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
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{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
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{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
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{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
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{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
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{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
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{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
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{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
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{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
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{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
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{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
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{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
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{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
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{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
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{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
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{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
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};
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static void tegra114_flush_dcache(struct page *page, unsigned long offset,
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1140
drivers/memory/tegra/tegra124-emc.c
Normal file
1140
drivers/memory/tegra/tegra124-emc.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -15,6 +15,48 @@
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#include "mc.h"
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
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#define MC_EMEM_ARB_TIMING_RCD 0x98
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#define MC_EMEM_ARB_TIMING_RP 0x9c
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#define MC_EMEM_ARB_TIMING_RC 0xa0
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#define MC_EMEM_ARB_TIMING_RAS 0xa4
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#define MC_EMEM_ARB_TIMING_FAW 0xa8
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#define MC_EMEM_ARB_TIMING_RRD 0xac
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#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
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#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
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#define MC_EMEM_ARB_TIMING_R2R 0xb8
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#define MC_EMEM_ARB_TIMING_W2W 0xbc
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#define MC_EMEM_ARB_TIMING_R2W 0xc0
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#define MC_EMEM_ARB_TIMING_W2R 0xc4
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#define MC_EMEM_ARB_DA_TURNS 0xd0
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#define MC_EMEM_ARB_DA_COVERS 0xd4
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ARB_MISC1 0xdc
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#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
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static const unsigned long tegra124_mc_emem_regs[] = {
|
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MC_EMEM_ARB_CFG,
|
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MC_EMEM_ARB_OUTSTANDING_REQ,
|
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MC_EMEM_ARB_TIMING_RCD,
|
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MC_EMEM_ARB_TIMING_RP,
|
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MC_EMEM_ARB_TIMING_RC,
|
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MC_EMEM_ARB_TIMING_RAS,
|
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MC_EMEM_ARB_TIMING_FAW,
|
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MC_EMEM_ARB_TIMING_RRD,
|
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MC_EMEM_ARB_TIMING_RAP2PRE,
|
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MC_EMEM_ARB_TIMING_WAP2PRE,
|
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MC_EMEM_ARB_TIMING_R2R,
|
||||
MC_EMEM_ARB_TIMING_W2W,
|
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MC_EMEM_ARB_TIMING_R2W,
|
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MC_EMEM_ARB_TIMING_W2R,
|
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MC_EMEM_ARB_DA_TURNS,
|
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MC_EMEM_ARB_DA_COVERS,
|
||||
MC_EMEM_ARB_MISC0,
|
||||
MC_EMEM_ARB_MISC1,
|
||||
MC_EMEM_ARB_RING1_THROTTLE
|
||||
};
|
||||
|
||||
static const struct tegra_mc_client tegra124_mc_clients[] = {
|
||||
{
|
||||
.id = 0x00,
|
||||
@@ -934,29 +976,29 @@ static const struct tegra_mc_client tegra124_mc_clients[] = {
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
|
||||
{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
|
||||
{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
|
||||
{ .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
|
||||
{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
|
||||
{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
|
||||
{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
|
||||
{ .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
|
||||
{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
|
||||
{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
|
||||
{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
|
||||
{ .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
|
||||
{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
|
||||
{ .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
|
||||
{ .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
|
||||
{ .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
|
||||
{ .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
|
||||
{ .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
|
||||
{ .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
|
||||
{ .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
|
||||
{ .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
|
||||
{ .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
|
||||
{ .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
|
||||
{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
|
||||
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
|
||||
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
|
||||
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
|
||||
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
|
||||
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
|
||||
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
|
||||
{ .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
|
||||
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
|
||||
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
|
||||
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
|
||||
{ .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
|
||||
{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
|
||||
{ .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
|
||||
{ .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
|
||||
{ .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
|
||||
{ .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
|
||||
{ .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
|
||||
{ .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
|
||||
{ .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
|
||||
{ .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
|
||||
{ .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
|
||||
{ .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
|
||||
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_124_SOC
|
||||
@@ -991,5 +1033,40 @@ const struct tegra_mc_soc tegra124_mc_soc = {
|
||||
.num_address_bits = 34,
|
||||
.atom_size = 32,
|
||||
.smmu = &tegra124_smmu_soc,
|
||||
.emem_regs = tegra124_mc_emem_regs,
|
||||
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_132_SOC
|
||||
static void tegra132_flush_dcache(struct page *page, unsigned long offset,
|
||||
size_t size)
|
||||
{
|
||||
void *virt = page_address(page) + offset;
|
||||
|
||||
__flush_dcache_area(virt, size);
|
||||
}
|
||||
|
||||
static const struct tegra_smmu_ops tegra132_smmu_ops = {
|
||||
.flush_dcache = tegra132_flush_dcache,
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_soc tegra132_smmu_soc = {
|
||||
.clients = tegra124_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
|
||||
.swgroups = tegra124_swgroups,
|
||||
.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
|
||||
.supports_round_robin_arbitration = true,
|
||||
.supports_request_limit = true,
|
||||
.num_asids = 128,
|
||||
.ops = &tegra132_smmu_ops,
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra132_mc_soc = {
|
||||
.clients = tegra124_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
|
||||
.num_address_bits = 34,
|
||||
.atom_size = 32,
|
||||
.smmu = &tegra132_smmu_soc,
|
||||
};
|
||||
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
|
||||
|
||||
@@ -918,22 +918,22 @@ static const struct tegra_mc_client tegra30_mc_clients[] = {
|
||||
};
|
||||
|
||||
static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
|
||||
{ .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
|
||||
{ .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
|
||||
{ .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
|
||||
{ .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
|
||||
{ .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
|
||||
{ .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
|
||||
{ .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
|
||||
{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
|
||||
{ .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
|
||||
{ .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
|
||||
{ .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
|
||||
{ .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
|
||||
{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
|
||||
{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
|
||||
{ .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
|
||||
{ .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
|
||||
{ .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
|
||||
{ .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
|
||||
{ .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
|
||||
{ .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
|
||||
{ .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
|
||||
{ .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
|
||||
{ .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
|
||||
{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
|
||||
{ .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
|
||||
{ .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
|
||||
{ .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
|
||||
{ .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
|
||||
{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
|
||||
{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
|
||||
{ .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
|
||||
{ .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
|
||||
};
|
||||
|
||||
static void tegra30_flush_dcache(struct page *page, unsigned long offset,
|
||||
|
||||
Reference in New Issue
Block a user