Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-meson' into clk-next
- Support qcom SM8150 RPMh clks - Set floor ops for qcom sd clks - Support qcom QCS404 WCSS clks - Support for Mediatek MT6779 SoCs - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) * clk-qcom: clk: qcom: rcg: Return failure for RCG update clk: qcom: fix QCS404 TuringCC regmap clk: qcom: clk-rpmh: Add support for SM8150 dt-bindings: clock: Document SM8150 rpmh-clock compatible clk: qcom: clk-rpmh: Convert to parent data scheme dt-bindings: clock: Document the parent clocks clk: qcom: gcc: Use floor ops for SDCC clocks clk: qcom: gcc-qcs404: Use floor ops for sdcc clks clk: qcom: gcc-sdm845: Use floor ops for sdcc clks clk: qcom: define probe by index API as common API clk: qcom: Add WCSS gcc clock control for QCS404 clk: qcom: msm8916: Don't build by default clk: qcom: gcc: Add global clock controller driver for SM8150 dt-bindings: clock: Document gcc bindings for SM8150 clk: qcom: clk-alpha-pll: Add support for Trion PLLs clk: qcom: clk-alpha-pll: Remove post_div_table checks clk: qcom: clk-alpha-pll: Remove unnecessary cast * clk-mtk: clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider clk: mediatek: Register clock gate with device clk: mediatek: add pericfg clocks for MT8183 dt-bindings: clock: mediatek: add pericfg for MT8183 clk: mediatek: Add MT6779 clock support clk: mediatek: Add dt-bindings for MT6779 clocks dt-bindings: mediatek: bindings for MT6779 clk clk: reset: Modify reset-controller driver * clk-armada: clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: mvebu: ap806: Fix clock name for the cluster clk: mvebu: add CPU clock driver for Armada 7K/8K clk: mvebu: add helper file for Armada AP and CP clocks dt-bindings: ap806: add the cluster clock node in the syscon file * clk-ingenic: clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro clk: ingenic/jz4740: Fix "pll half" divider not read/written properly * clk-meson: (23 commits) clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock clk: meson: g12a: add support for SM1 GP1 PLL dt-bindings: clk: meson: add sm1 periph clock controller bindings clk: meson: axg-audio: add g12a reset support dt-bindings: clock: meson: add resets to the audio clock controller clk: meson: g12a: expose CPUB clock ID for G12B clk: meson: g12a: add notifiers to handle cpu clock change clk: meson: add g12a cpu dynamic divider driver clk: core: introduce clk_hw_set_parent() clk: meson: remove clk input helper clk: meson: remove ee input bypass clocks clk: meson: clk-regmap: migrate to new parent description method clk: meson: meson8b: migrate to the new parent description method clk: meson: axg: migrate to the new parent description method clk: meson: gxbb: migrate to the new parent description method clk: meson: g12a: migrate to the new parent description method clk: meson: remove ao input bypass clocks clk: meson: axg-aoclk: migrate to the new parent description method clk: meson: gxbb-aoclk: migrate to the new parent description method ...
This commit is contained in:
Stephen Boyd
@@ -18,17 +18,19 @@ Clocks:
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-------
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The Device Tree node representing the AP806 system controller provides
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a number of clocks:
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The Device Tree node representing the AP806/AP807 system controller
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provides a number of clocks:
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- 0: clock of CPU cluster 0
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- 1: clock of CPU cluster 1
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- 0: reference clock of CPU cluster 0
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- 1: reference clock of CPU cluster 1
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- 2: fixed PLL at 1200 Mhz
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- 3: MSS clock, derived from the fixed PLL
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Required properties:
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- compatible: must be: "marvell,ap806-clock"
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- compatible: must be one of:
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* "marvell,ap806-clock"
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* "marvell,ap807-clock"
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- #clock-cells: must be set to 1
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Pinctrl:
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@@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 {
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#thermal-sensor-cells = <1>;
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};
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};
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Cluster clocks:
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---------------
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Device Tree Clock bindings for cluster clock of Marvell
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AP806/AP807. Each cluster contain up to 2 CPUs running at the same
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frequency.
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Required properties:
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- compatible: must be one of:
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* "marvell,ap806-cpu-clock"
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* "marvell,ap807-cpu-clock"
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock(s) phandle for the clock
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(one per cluster)
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- reg: register range associated with the cluster clocks
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ap_syscon1: system-controller@6f8000 {
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compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
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reg = <0x6f8000 0x1000>;
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cpu_clk: clock-cpu@278 {
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compatible = "marvell,ap806-cpu-clock";
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clocks = <&ap_clk 0>, <&ap_clk 1>;
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#clock-cells = <1>;
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reg = <0x278 0xa30>;
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};
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};
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-apmixedsys"
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6779-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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- "mediatek,mt7622-apmixedsys"
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- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt6779-audio", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt8183-audiosys", "syscon"
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@@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt6779-camsys", "syscon"
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- "mediatek,mt8183-camsys", "syscon"
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- #clock-cells: Must be 1
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6779-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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@@ -9,6 +9,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6779-infracfg_ao", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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@@ -0,0 +1,22 @@
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Mediatek ipesys controller
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============================
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The Mediatek ipesys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt6779-ipesys", "syscon"
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- #clock-cells: Must be 1
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The ipesys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ipesys: clock-controller@1b000000 {
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compatible = "mediatek,mt6779-ipesys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mfgcfg", "syscon"
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- "mediatek,mt6779-mfgcfg", "syscon"
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- "mediatek,mt8183-mfgcfg", "syscon"
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- #clock-cells: Must be 1
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt2712-mmsys", "syscon"
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- "mediatek,mt6779-mmsys", "syscon"
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- "mediatek,mt6797-mmsys", "syscon"
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- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt8173-mmsys", "syscon"
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@@ -14,6 +14,7 @@ Required Properties:
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- "mediatek,mt7629-pericfg", "syscon"
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- "mediatek,mt8135-pericfg", "syscon"
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- "mediatek,mt8173-pericfg", "syscon"
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- "mediatek,mt8183-pericfg", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-topckgen"
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- "mediatek,mt2712-topckgen", "syscon"
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- "mediatek,mt6779-topckgen", "syscon"
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- "mediatek,mt6797-topckgen"
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- "mediatek,mt7622-topckgen"
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- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt2712-vdecsys", "syscon"
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- "mediatek,mt6779-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-vencsys", "syscon"
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- "mediatek,mt6779-vencsys", "syscon"
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- "mediatek,mt6797-vencsys", "syscon"
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- "mediatek,mt8173-vencsys", "syscon"
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- "mediatek,mt8183-vencsys", "syscon"
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@@ -22,6 +22,7 @@ Required Properties:
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components.
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- resets : phandle of the internal reset line
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- #clock-cells : should be 1.
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- #reset-cells : should be 1 on the g12a (and following) soc family
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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@@ -11,6 +11,7 @@ Required Properties:
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"amlogic,axg-clkc" for AXG SoC.
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"amlogic,g12a-clkc" for G12A SoC.
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"amlogic,g12b-clkc" for G12B SoC.
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"amlogic,sm1-clkc" for SM1 SoC.
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- clocks : list of clock phandle, one for each entry clock-names.
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- clock-names : should contain the following:
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* "xtal": the platform xtal
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@@ -23,6 +23,7 @@ Required properties :
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"qcom,gcc-sdm630"
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"qcom,gcc-sdm660"
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"qcom,gcc-sdm845"
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"qcom,gcc-sm8150"
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- reg : shall contain base register location and length
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- #clock-cells : shall contain 1
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@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
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- protected-clocks : Protected clock specifier list as per common clock
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binding.
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For SM8150 only:
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: "bi_tcxo" (required)
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"sleep_clk" (optional)
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"aud_ref_clock" (optional)
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Example:
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clock-controller@900000 {
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compatible = "qcom,gcc-msm8960";
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@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
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<GCC_LPASS_Q6_AXI_CLK>,
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<GCC_LPASS_SWAY_CLK>;
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};
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Example of GCC with clocks
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sm8150";
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reg = <0x00100000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo",
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"sleep_clk";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&sleep_clk>;
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};
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@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
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other hardware subsystems via RSC to control clocks.
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Required properties :
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- compatible : shall contain "qcom,sdm845-rpmh-clk"
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- compatible : must be one of:
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"qcom,sdm845-rpmh-clk"
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"qcom,sm8150-rpmh-clk"
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- #clock-cells : must contain 1
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: Parent board clock: "xo".
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Example :
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