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Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Browse Source 
Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...
This commit is contained in:
Linus Torvalds
2018-04-02 20:20:12 -07:00
parent c9297d2841 dd3b8c329a
commit f5a8eb632b
2498 changed files with 95 additions and 467668 deletions
Download Patch File Download Diff File Expand all files Collapse all files

198
drivers/tty/serial/Kconfig
View File

@@ -498,92 +498,6 @@ config SERIAL_SA1100_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
config SERIAL_BFIN
tristate "Blackfin serial port support"
depends on BLACKFIN
select SERIAL_CORE
select SERIAL_BFIN_UART0 if (BF531 || BF532 || BF533 || BF561)
help
Add support for the built-in UARTs on the Blackfin.
To compile this driver as a module, choose M here: the
module is named bfin_uart.ko.
config SERIAL_BFIN_CONSOLE
bool "Console on Blackfin serial port"
depends on SERIAL_BFIN=y
select SERIAL_CORE_CONSOLE
choice
prompt "UART Mode"
depends on SERIAL_BFIN
default SERIAL_BFIN_DMA
help
This driver supports the built-in serial ports of the Blackfin family
of CPUs
config SERIAL_BFIN_DMA
bool "DMA mode"
depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n
help
This driver works under DMA mode. If this option is selected, the
blackfin simple dma driver is also enabled.
config SERIAL_BFIN_PIO
bool "PIO mode"
help
This driver works under PIO mode.
endchoice
config SERIAL_BFIN_UART0
bool "Enable UART0"
depends on SERIAL_BFIN
help
Enable UART0
config BFIN_UART0_CTSRTS
bool "Enable UART0 hardware flow control"
depends on SERIAL_BFIN_UART0
help
Enable hardware flow control in the driver.
config SERIAL_BFIN_UART1
bool "Enable UART1"
depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561)
help
Enable UART1
config BFIN_UART1_CTSRTS
bool "Enable UART1 hardware flow control"
depends on SERIAL_BFIN_UART1
help
Enable hardware flow control in the driver.
config SERIAL_BFIN_UART2
bool "Enable UART2"
depends on SERIAL_BFIN && (BF54x || BF538 || BF539)
help
Enable UART2
config BFIN_UART2_CTSRTS
bool "Enable UART2 hardware flow control"
depends on SERIAL_BFIN_UART2
help
Enable hardware flow control in the driver.
config SERIAL_BFIN_UART3
bool "Enable UART3"
depends on SERIAL_BFIN && (BF54x)
help
Enable UART3
config BFIN_UART3_CTSRTS
bool "Enable UART3 hardware flow control"
depends on SERIAL_BFIN_UART3
help
Enable hardware flow control in the driver.
config SERIAL_IMX
tristate "IMX serial port support"
depends on HAS_DMA
@@ -991,35 +905,6 @@ config SERIAL_ICOM
This driver can also be built as a module. If so, the module
will be called icom.
config SERIAL_M32R_SIO
bool "M32R SIO I/F"
depends on M32R
default y
select SERIAL_CORE
help
Say Y here if you want to use the M32R serial controller.
config SERIAL_M32R_SIO_CONSOLE
bool "use SIO console"
depends on SERIAL_M32R_SIO=y
select SERIAL_CORE_CONSOLE
help
Say Y here if you want to support a serial console.
If you use an M3T-M32700UT or an OPSPUT platform,
please say also y for SERIAL_M32R_PLDSIO.
config SERIAL_M32R_PLDSIO
bool "M32R SIO I/F on a PLD"
depends on SERIAL_M32R_SIO=y && (PLAT_OPSPUT || PLAT_USRV || PLAT_M32700UT)
default n
help
Say Y here if you want to use the M32R serial controller
on a PLD (Programmable Logic Device).
If you use an M3T-M32700UT or an OPSPUT platform,
please say Y.
config SERIAL_TXX9
bool "TMPTX39XX/49XX SIO support"
depends on HAS_TXX9_SERIAL
@@ -1114,17 +999,6 @@ config SERIAL_VT8500_CONSOLE
depends on SERIAL_VT8500=y
select SERIAL_CORE_CONSOLE
config SERIAL_ETRAXFS
bool "ETRAX FS serial port support"
depends on ETRAX_ARCH_V32 && OF
select SERIAL_CORE
select SERIAL_MCTRL_GPIO if GPIOLIB
config SERIAL_ETRAXFS_CONSOLE
bool "ETRAX FS serial console support"
depends on SERIAL_ETRAXFS
select SERIAL_CORE_CONSOLE
config SERIAL_NETX
tristate "NetX serial port support"
depends on ARCH_NETX
@@ -1242,69 +1116,6 @@ config SERIAL_SC16IS7XX_SPI
This is additional support to exsisting driver.
You must select at least one bus for the driver to be built.
config SERIAL_BFIN_SPORT
tristate "Blackfin SPORT emulate UART"
depends on BLACKFIN
select SERIAL_CORE
help
Enable SPORT emulate UART on Blackfin series.
To compile this driver as a module, choose M here: the
module will be called bfin_sport_uart.
config SERIAL_BFIN_SPORT_CONSOLE
bool "Console on Blackfin sport emulated uart"
depends on SERIAL_BFIN_SPORT=y
select SERIAL_CORE_CONSOLE
config SERIAL_BFIN_SPORT0_UART
bool "Enable UART over SPORT0"
depends on SERIAL_BFIN_SPORT && !(BF542 || BF544)
help
Enable UART over SPORT0
config SERIAL_BFIN_SPORT0_UART_CTSRTS
bool "Enable UART over SPORT0 hardware flow control"
depends on SERIAL_BFIN_SPORT0_UART
help
Enable hardware flow control in the driver.
config SERIAL_BFIN_SPORT1_UART
bool "Enable UART over SPORT1"
depends on SERIAL_BFIN_SPORT
help
Enable UART over SPORT1
config SERIAL_BFIN_SPORT1_UART_CTSRTS
bool "Enable UART over SPORT1 hardware flow control"
depends on SERIAL_BFIN_SPORT1_UART
help
Enable hardware flow control in the driver.
config SERIAL_BFIN_SPORT2_UART
bool "Enable UART over SPORT2"
depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
help
Enable UART over SPORT2
config SERIAL_BFIN_SPORT2_UART_CTSRTS
bool "Enable UART over SPORT2 hardware flow control"
depends on SERIAL_BFIN_SPORT2_UART
help
Enable hardware flow control in the driver.
config SERIAL_BFIN_SPORT3_UART
bool "Enable UART over SPORT3"
depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)
help
Enable UART over SPORT3
config SERIAL_BFIN_SPORT3_UART_CTSRTS
bool "Enable UART over SPORT3 hardware flow control"
depends on SERIAL_BFIN_SPORT3_UART
help
Enable hardware flow control in the driver.
config SERIAL_TIMBERDALE
tristate "Support for timberdale UART"
select SERIAL_CORE
@@ -1519,15 +1330,6 @@ config SERIAL_EFM32_UART_CONSOLE
depends on SERIAL_EFM32_UART=y
select SERIAL_CORE_CONSOLE
config SERIAL_TILEGX
tristate "TILE-Gx on-chip serial port support"
depends on TILEGX
select TILE_GXIO_UART
select SERIAL_CORE
---help---
This device provides access to the on-chip UARTs on the TILE-Gx
processor.
config SERIAL_ARC
tristate "ARC UART driver support"
select SERIAL_CORE

6
drivers/tty/serial/Makefile
View File

@@ -29,8 +29,6 @@ obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o
obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o
obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o
obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o
obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o
obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
obj-$(CONFIG_SERIAL_MAX310X) += max310x.o
@@ -47,12 +45,9 @@ obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
obj-$(CONFIG_SERIAL_IMX) += imx.o
obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
obj-$(CONFIG_SERIAL_ICOM) += icom.o
obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
obj-$(CONFIG_SERIAL_MESON) += meson_uart.o
obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o
obj-$(CONFIG_SERIAL_ETRAXFS) += etraxfs-uart.o
obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o
obj-$(CONFIG_SERIAL_SC16IS7XX_CORE) += sc16is7xx.o
obj-$(CONFIG_SERIAL_JSM) += jsm/
@@ -68,7 +63,6 @@ obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
obj-$(CONFIG_SERIAL_ST_ASC) += st-asc.o
obj-$(CONFIG_SERIAL_TILEGX) += tilegx.o
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o

937
drivers/tty/serial/bfin_sport_uart.c
View File

@@ -1,937 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Blackfin On-Chip Sport Emulated UART Driver
*
* Copyright 2006-2009 Analog Devices Inc.
*
* Enter bugs at http://blackfin.uclinux.org/
*/
/*
* This driver and the hardware supported are in term of EE-191 of ADI.
* http://www.analog.com/static/imported-files/application_notes/EE191.pdf
* This application note describe how to implement a UART on a Sharc DSP,
* but this driver is implemented on Blackfin Processor.
* Transmit Frame Sync is not used by this driver to transfer data out.
*/
/* #define DEBUG */
#define DRV_NAME "bfin-sport-uart"
#define DEVICE_NAME "ttySS"
#define pr_fmt(fmt) DRV_NAME ": " fmt
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/gpio.h>
#include <asm/bfin_sport.h>
#include <asm/delay.h>
#include <asm/portmux.h>
#include "bfin_sport_uart.h"
struct sport_uart_port {
struct uart_port port;
int err_irq;
unsigned short csize;
unsigned short rxmask;
unsigned short txmask1;
unsigned short txmask2;
unsigned char stopb;
/* unsigned char parib; */
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
int cts_pin;
int rts_pin;
#endif
};
static int sport_uart_tx_chars(struct sport_uart_port *up);
static void sport_stop_tx(struct uart_port *port);
static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
{
pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
up->txmask1, up->txmask2);
/* Place Start and Stop bits */
__asm__ __volatile__ (
"%[val] <<= 1;"
"%[val] = %[val] & %[mask1];"
"%[val] = %[val] | %[mask2];"
: [val]"+d"(value)
: [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
: "ASTAT"
);
pr_debug("%s value:%x\n", __func__, value);
SPORT_PUT_TX(up, value);
}
static inline unsigned char rx_one_byte(struct sport_uart_port *up)
{
unsigned int value;
unsigned char extract;
u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
if ((up->csize + up->stopb) > 7)
value = SPORT_GET_RX32(up);
else
value = SPORT_GET_RX(up);
pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
up->csize, up->rxmask);
/* Extract data */
__asm__ __volatile__ (
"%[extr] = 0;"
"%[mask1] = %[rxmask];"
"%[mask2] = 0x0200(Z);"
"%[shift] = 0;"
"LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
".Lloop_s:"
"%[tmp] = extract(%[val], %[mask1].L)(Z);"
"%[tmp] <<= %[shift];"
"%[extr] = %[extr] | %[tmp];"
"%[mask1] = %[mask1] - %[mask2];"
".Lloop_e:"
"%[shift] += 1;"
: [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
[mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
: [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
: "ASTAT", "LB0", "LC0", "LT0"
);
pr_debug(" extract:%x\n", extract);
return extract;
}
static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
{
int tclkdiv, rclkdiv;
unsigned int sclk = get_sclk();
/* Set TCR1 and TCR2, TFSR is not enabled for uart */
SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
SPORT_PUT_TCR2(up, size + 1);
pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
/* Set RCR1 and RCR2 */
SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
tclkdiv = sclk / (2 * baud_rate) - 1;
/* The actual uart baud rate of devices vary between +/-2%. The sport
* RX sample rate should be faster than the double of the worst case,
* otherwise, wrong data are received. So, set sport RX clock to be
* 3% faster.
*/
rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
SPORT_PUT_TCLKDIV(up, tclkdiv);
SPORT_PUT_RCLKDIV(up, rclkdiv);
SSYNC();
pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
__func__, sclk, baud_rate, tclkdiv, rclkdiv);
return 0;
}
static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
{
struct sport_uart_port *up = dev_id;
struct tty_port *port = &up->port.state->port;
unsigned int ch;
spin_lock(&up->port.lock);
while (SPORT_GET_STAT(up) & RXNE) {
ch = rx_one_byte(up);
up->port.icount.rx++;
if (!uart_handle_sysrq_char(&up->port, ch))
tty_insert_flip_char(port, ch, TTY_NORMAL);
}
spin_unlock(&up->port.lock);
/* XXX this won't deadlock with lowlat? */
tty_flip_buffer_push(port);
return IRQ_HANDLED;
}
static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
{
struct sport_uart_port *up = dev_id;
spin_lock(&up->port.lock);
sport_uart_tx_chars(up);
spin_unlock(&up->port.lock);
return IRQ_HANDLED;
}
static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
{
struct sport_uart_port *up = dev_id;
unsigned int stat = SPORT_GET_STAT(up);
spin_lock(&up->port.lock);
/* Overflow in RX FIFO */
if (stat & ROVF) {
up->port.icount.overrun++;
tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN);
SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
}
/* These should not happen */
if (stat & (TOVF | TUVF | RUVF)) {
pr_err("SPORT Error:%s %s %s\n",
(stat & TOVF) ? "TX overflow" : "",
(stat & TUVF) ? "TX underflow" : "",
(stat & RUVF) ? "RX underflow" : "");
SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
}
SSYNC();
spin_unlock(&up->port.lock);
/* XXX we don't push the overrun bit to TTY? */
return IRQ_HANDLED;
}
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
static unsigned int sport_get_mctrl(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
if (up->cts_pin < 0)
return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
/* CTS PIN is negative assertive. */
if (SPORT_UART_GET_CTS(up))
return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
else
return TIOCM_DSR | TIOCM_CAR;
}
static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
if (up->rts_pin < 0)
return;
/* RTS PIN is negative assertive. */
if (mctrl & TIOCM_RTS)
SPORT_UART_ENABLE_RTS(up);
else
SPORT_UART_DISABLE_RTS(up);
}
/*
* Handle any change of modem status signal.
*/
static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
{
struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
unsigned int status;
status = sport_get_mctrl(&up->port);
uart_handle_cts_change(&up->port, status & TIOCM_CTS);
return IRQ_HANDLED;
}
#else
static unsigned int sport_get_mctrl(struct uart_port *port)
{
pr_debug("%s enter\n", __func__);
return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
}
static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
pr_debug("%s enter\n", __func__);
}
#endif
/* Reqeust IRQ, Setup clock */
static int sport_startup(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
int ret;
pr_debug("%s enter\n", __func__);
ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
"SPORT_UART_RX", up);
if (ret) {
dev_err(port->dev, "unable to request SPORT RX interrupt\n");
return ret;
}
ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
"SPORT_UART_TX", up);
if (ret) {
dev_err(port->dev, "unable to request SPORT TX interrupt\n");
goto fail1;
}
ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
"SPORT_UART_STATUS", up);
if (ret) {
dev_err(port->dev, "unable to request SPORT status interrupt\n");
goto fail2;
}
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
if (up->cts_pin >= 0) {
if (request_irq(gpio_to_irq(up->cts_pin),
sport_mctrl_cts_int,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
0, "BFIN_SPORT_UART_CTS", up)) {
up->cts_pin = -1;
dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
}
}
if (up->rts_pin >= 0) {
if (gpio_request(up->rts_pin, DRV_NAME)) {
dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin);
up->rts_pin = -1;
} else
gpio_direction_output(up->rts_pin, 0);
}
#endif
return 0;
fail2:
free_irq(up->port.irq+1, up);
fail1:
free_irq(up->port.irq, up);
return ret;
}
/*
* sport_uart_tx_chars
*
* ret 1 means need to enable sport.
* ret 0 means do nothing.
*/
static int sport_uart_tx_chars(struct sport_uart_port *up)
{
struct circ_buf *xmit = &up->port.state->xmit;
if (SPORT_GET_STAT(up) & TXF)
return 0;
if (up->port.x_char) {
tx_one_byte(up, up->port.x_char);
up->port.icount.tx++;
up->port.x_char = 0;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
/* The waiting loop to stop SPORT TX from TX interrupt is
* too long. This may block SPORT RX interrupts and cause
* RX FIFO overflow. So, do stop sport TX only after the last
* char in TX FIFO is moved into the shift register.
*/
if (SPORT_GET_STAT(up) & TXHRE)
sport_stop_tx(&up->port);
return 0;
}
while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
tx_one_byte(up, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
up->port.icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
return 1;
}
static unsigned int sport_tx_empty(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
unsigned int stat;
stat = SPORT_GET_STAT(up);
pr_debug("%s stat:%04x\n", __func__, stat);
if (stat & TXHRE) {
return TIOCSER_TEMT;
} else
return 0;
}
static void sport_stop_tx(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
pr_debug("%s enter\n", __func__);
if (!(SPORT_GET_TCR1(up) & TSPEN))
return;
/* Although the hold register is empty, last byte is still in shift
* register and not sent out yet. So, put a dummy data into TX FIFO.
* Then, sport tx stops when last byte is shift out and the dummy
* data is moved into the shift register.
*/
SPORT_PUT_TX(up, 0xffff);
while (!(SPORT_GET_STAT(up) & TXHRE))
cpu_relax();
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
SSYNC();
return;
}
static void sport_start_tx(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
pr_debug("%s enter\n", __func__);
/* Write data into SPORT FIFO before enable SPROT to transmit */
if (sport_uart_tx_chars(up)) {
/* Enable transmit, then an interrupt will generated */
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
SSYNC();
}
pr_debug("%s exit\n", __func__);
}
static void sport_stop_rx(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
pr_debug("%s enter\n", __func__);
/* Disable sport to stop rx */
SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
SSYNC();
}
static void sport_break_ctl(struct uart_port *port, int break_state)
{
pr_debug("%s enter\n", __func__);
}
static void sport_shutdown(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
dev_dbg(port->dev, "%s enter\n", __func__);
/* Disable sport */
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
SSYNC();
free_irq(up->port.irq, up);
free_irq(up->port.irq+1, up);
free_irq(up->err_irq, up);
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
if (up->cts_pin >= 0)
free_irq(gpio_to_irq(up->cts_pin), up);
if (up->rts_pin >= 0)
gpio_free(up->rts_pin);
#endif
}
static const char *sport_type(struct uart_port *port)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
pr_debug("%s enter\n", __func__);
return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
}
static void sport_release_port(struct uart_port *port)
{
pr_debug("%s enter\n", __func__);
}
static int sport_request_port(struct uart_port *port)
{
pr_debug("%s enter\n", __func__);
return 0;
}
static void sport_config_port(struct uart_port *port, int flags)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
pr_debug("%s enter\n", __func__);
up->port.type = PORT_BFIN_SPORT;
}
static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
{
pr_debug("%s enter\n", __func__);
return 0;
}
static void sport_set_termios(struct uart_port *port,
struct ktermios *termios, struct ktermios *old)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
unsigned long flags;
int i;
pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
if (old == NULL && up->cts_pin != -1)
termios->c_cflag |= CRTSCTS;
else if (up->cts_pin == -1)
termios->c_cflag &= ~CRTSCTS;
#endif
switch (termios->c_cflag & CSIZE) {
case CS8:
up->csize = 8;
break;
case CS7:
up->csize = 7;
break;
case CS6:
up->csize = 6;
break;
case CS5:
up->csize = 5;
break;
default:
pr_warn("requested word length not supported\n");
break;
}
if (termios->c_cflag & CSTOPB) {
up->stopb = 1;
}
if (termios->c_cflag & PARENB) {
pr_warn("PAREN bit is not supported yet\n");
/* up->parib = 1; */
}
spin_lock_irqsave(&up->port.lock, flags);
port->read_status_mask = 0;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
/* RX extract mask */
up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
/* TX masks, 8 bit data and 1 bit stop for example:
* mask1 = b#0111111110
* mask2 = b#1000000000
*/
for (i = 0, up->txmask1 = 0; i < up->csize; i++)
up->txmask1 |= (1<<i);
up->txmask2 = (1<<i);
if (up->stopb) {
++i;
up->txmask2 |= (1<<i);
}
up->txmask1 <<= 1;
up->txmask2 <<= 1;
/* uart baud rate */
port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
/* Disable UART */
SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
/* driver TX line high after config, one dummy data is
* necessary to stop sport after shift one byte
*/
SPORT_PUT_TX(up, 0xffff);
SPORT_PUT_TX(up, 0xffff);
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
SSYNC();
while (!(SPORT_GET_STAT(up) & TXHRE))
cpu_relax();
SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
SSYNC();
/* Port speed changed, update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, port->uartclk);
/* Enable sport rx */
SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
SSYNC();
spin_unlock_irqrestore(&up->port.lock, flags);
}
static const struct uart_ops sport_uart_ops = {
.tx_empty = sport_tx_empty,
.set_mctrl = sport_set_mctrl,
.get_mctrl = sport_get_mctrl,
.stop_tx = sport_stop_tx,
.start_tx = sport_start_tx,
.stop_rx = sport_stop_rx,
.break_ctl = sport_break_ctl,
.startup = sport_startup,
.shutdown = sport_shutdown,
.set_termios = sport_set_termios,
.type = sport_type,
.release_port = sport_release_port,
.request_port = sport_request_port,
.config_port = sport_config_port,
.verify_port = sport_verify_port,
};
#define BFIN_SPORT_UART_MAX_PORTS 4
static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
static int __init
sport_uart_console_setup(struct console *co, char *options)
{
struct sport_uart_port *up;
int baud = 57600;
int bits = 8;
int parity = 'n';
# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
int flow = 'r';
# else
int flow = 'n';
# endif
/* Check whether an invalid uart number has been specified */
if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
return -ENODEV;
up = bfin_sport_uart_ports[co->index];
if (!up)
return -ENODEV;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(&up->port, co, baud, parity, bits, flow);
}
static void sport_uart_console_putchar(struct uart_port *port, int ch)
{
struct sport_uart_port *up = (struct sport_uart_port *)port;
while (SPORT_GET_STAT(up) & TXF)
barrier();
tx_one_byte(up, ch);
}
/*
* Interrupts are disabled on entering
*/
static void
sport_uart_console_write(struct console *co, const char *s, unsigned int count)
{
struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
if (SPORT_GET_TCR1(up) & TSPEN)
uart_console_write(&up->port, s, count, sport_uart_console_putchar);
else {
/* dummy data to start sport */
while (SPORT_GET_STAT(up) & TXF)
barrier();
SPORT_PUT_TX(up, 0xffff);
/* Enable transmit, then an interrupt will generated */
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
SSYNC();
uart_console_write(&up->port, s, count, sport_uart_console_putchar);
/* Although the hold register is empty, last byte is still in shift
* register and not sent out yet. So, put a dummy data into TX FIFO.
* Then, sport tx stops when last byte is shift out and the dummy
* data is moved into the shift register.
*/
while (SPORT_GET_STAT(up) & TXF)
barrier();
SPORT_PUT_TX(up, 0xffff);
while (!(SPORT_GET_STAT(up) & TXHRE))
barrier();
/* Stop sport tx transfer */
SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
SSYNC();
}
spin_unlock_irqrestore(&up->port.lock, flags);
}
static struct uart_driver sport_uart_reg;
static struct console sport_uart_console = {
.name = DEVICE_NAME,
.write = sport_uart_console_write,
.device = uart_console_device,
.setup = sport_uart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &sport_uart_reg,
};
#define SPORT_UART_CONSOLE (&sport_uart_console)
#else
#define SPORT_UART_CONSOLE NULL
#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
static struct uart_driver sport_uart_reg = {
.owner = THIS_MODULE,
.driver_name = DRV_NAME,
.dev_name = DEVICE_NAME,
.major = 204,
.minor = 84,
.nr = BFIN_SPORT_UART_MAX_PORTS,
.cons = SPORT_UART_CONSOLE,
};
#ifdef CONFIG_PM
static int sport_uart_suspend(struct device *dev)
{
struct sport_uart_port *sport = dev_get_drvdata(dev);
dev_dbg(dev, "%s enter\n", __func__);
if (sport)
uart_suspend_port(&sport_uart_reg, &sport->port);
return 0;
}
static int sport_uart_resume(struct device *dev)
{
struct sport_uart_port *sport = dev_get_drvdata(dev);
dev_dbg(dev, "%s enter\n", __func__);
if (sport)
uart_resume_port(&sport_uart_reg, &sport->port);
return 0;
}
static const struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
.suspend = sport_uart_suspend,
.resume = sport_uart_resume,
};
#endif
static int sport_uart_probe(struct platform_device *pdev)
{
struct resource *res;
struct sport_uart_port *sport;
int ret = 0;
dev_dbg(&pdev->dev, "%s enter\n", __func__);
if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
return -ENOENT;
}
if (bfin_sport_uart_ports[pdev->id] == NULL) {
bfin_sport_uart_ports[pdev->id] =
kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
sport = bfin_sport_uart_ports[pdev->id];
if (!sport) {
dev_err(&pdev->dev,
"Fail to malloc sport_uart_port\n");
return -ENOMEM;
}
ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
DRV_NAME);
if (ret) {
dev_err(&pdev->dev,
"Fail to request SPORT peripherals\n");
goto out_error_free_mem;
}
spin_lock_init(&sport->port.lock);
sport->port.fifosize = SPORT_TX_FIFO_SIZE,
sport->port.ops = &sport_uart_ops;
sport->port.line = pdev->id;
sport->port.iotype = UPIO_MEM;
sport->port.flags = UPF_BOOT_AUTOCONF;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
ret = -ENOENT;
goto out_error_free_peripherals;
}
sport->port.membase = ioremap(res->start, resource_size(res));
if (!sport->port.membase) {
dev_err(&pdev->dev, "Cannot map sport IO\n");
ret = -ENXIO;
goto out_error_free_peripherals;
}
sport->port.mapbase = res->start;
sport->port.irq = platform_get_irq(pdev, 0);
if ((int)sport->port.irq < 0) {
dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
ret = -ENOENT;
goto out_error_unmap;
}
sport->err_irq = platform_get_irq(pdev, 1);
if (sport->err_irq < 0) {
dev_err(&pdev->dev, "No sport status IRQ specified\n");
ret = -ENOENT;
goto out_error_unmap;
}
#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (res == NULL)
sport->cts_pin = -1;
else
sport->cts_pin = res->start;
res = platform_get_resource(pdev, IORESOURCE_IO, 1);
if (res == NULL)
sport->rts_pin = -1;
else
sport->rts_pin = res->start;
#endif
}
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
if (!is_early_platform_device(pdev)) {
#endif
sport = bfin_sport_uart_ports[pdev->id];
sport->port.dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, sport);
ret = uart_add_one_port(&sport_uart_reg, &sport->port);
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
}
#endif
if (!ret)
return 0;
if (sport) {
out_error_unmap:
iounmap(sport->port.membase);
out_error_free_peripherals:
peripheral_free_list(dev_get_platdata(&pdev->dev));
out_error_free_mem:
kfree(sport);
bfin_sport_uart_ports[pdev->id] = NULL;
}
return ret;
}
static int sport_uart_remove(struct platform_device *pdev)
{
struct sport_uart_port *sport = platform_get_drvdata(pdev);
dev_dbg(&pdev->dev, "%s enter\n", __func__);
dev_set_drvdata(&pdev->dev, NULL);
if (sport) {
uart_remove_one_port(&sport_uart_reg, &sport->port);
iounmap(sport->port.membase);
peripheral_free_list(dev_get_platdata(&pdev->dev));
kfree(sport);
bfin_sport_uart_ports[pdev->id] = NULL;
}
return 0;
}
static struct platform_driver sport_uart_driver = {
.probe = sport_uart_probe,
.remove = sport_uart_remove,
.driver = {
.name = DRV_NAME,
#ifdef CONFIG_PM
.pm = &bfin_sport_uart_dev_pm_ops,
#endif
},
};
#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
static struct early_platform_driver early_sport_uart_driver __initdata = {
.class_str = CLASS_BFIN_SPORT_CONSOLE,
.pdrv = &sport_uart_driver,
.requested_id = EARLY_PLATFORM_ID_UNSET,
};
static int __init sport_uart_rs_console_init(void)
{
early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
BFIN_SPORT_UART_MAX_PORTS, 0);
register_console(&sport_uart_console);
return 0;
}
console_initcall(sport_uart_rs_console_init);
#endif
static int __init sport_uart_init(void)
{
int ret;
pr_info("Blackfin uart over sport driver\n");
ret = uart_register_driver(&sport_uart_reg);
if (ret) {
pr_err("failed to register %s:%d\n",
sport_uart_reg.driver_name, ret);
return ret;
}
ret = platform_driver_register(&sport_uart_driver);
if (ret) {
pr_err("failed to register sport uart driver:%d\n", ret);
uart_unregister_driver(&sport_uart_reg);
}
return ret;
}
module_init(sport_uart_init);
static void __exit sport_uart_exit(void)
{
platform_driver_unregister(&sport_uart_driver);
uart_unregister_driver(&sport_uart_reg);
}
module_exit(sport_uart_exit);
MODULE_AUTHOR("Sonic Zhang, Roy Huang");
MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
MODULE_LICENSE("GPL");

86
drivers/tty/serial/bfin_sport_uart.h
View File

@@ -1,86 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Blackfin On-Chip Sport Emulated UART Driver
*
* Copyright 2006-2008 Analog Devices Inc.
*
* Enter bugs at http://blackfin.uclinux.org/
*/
/*
* This driver and the hardware supported are in term of EE-191 of ADI.
* http://www.analog.com/static/imported-files/application_notes/EE191.pdf
* This application note describe how to implement a UART on a Sharc DSP,
* but this driver is implemented on Blackfin Processor.
* Transmit Frame Sync is not used by this driver to transfer data out.
*/
#ifndef _BFIN_SPORT_UART_H
#define _BFIN_SPORT_UART_H
#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
#define OFFSET_TX 0x10 /* Transmit Data Register */
#define OFFSET_RX 0x18 /* Receive Data Register */
#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
#define OFFSET_STAT 0x30 /* Status Register */
#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
/*
* If another interrupt fires while doing a 32-bit read from RX FIFO,
* a fake RX underflow error will be generated. So disable interrupts
* to prevent interruption while reading the FIFO.
*/
#define SPORT_GET_RX32(sport) \
({ \
unsigned int __ret; \
unsigned long flags; \
if (ANOMALY_05000473) \
local_irq_save(flags); \
__ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
if (ANOMALY_05000473) \
local_irq_restore(flags); \
__ret; \
})
#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
#define SPORT_TX_FIFO_SIZE 8
#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin)
#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \
|| defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \
|| defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \
|| defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)
# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS
#endif
#endif /* _BFIN_SPORT_UART_H */

1551
drivers/tty/serial/bfin_uart.c
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File diff suppressed because it is too large Load Diff

4248
drivers/tty/serial/crisv10.c
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File diff suppressed because it is too large Load Diff

133
drivers/tty/serial/crisv10.h
View File

@@ -1,133 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* serial.h: Arch-dep definitions for the Etrax100 serial driver.
*
* Copyright (C) 1998-2007 Axis Communications AB
*/
#ifndef _ETRAX_SERIAL_H
#define _ETRAX_SERIAL_H
#include <linux/circ_buf.h>
#include <asm/termios.h>
#include <asm/dma.h>
#include <arch/io_interface_mux.h>
/* Software state per channel */
#ifdef __KERNEL__
/*
* This is our internal structure for each serial port's state.
*
* Many fields are paralleled by the structure used by the serial_struct
* structure.
*
* For definitions of the flags field, see tty.h
*/
#define SERIAL_RECV_DESCRIPTORS 8
struct etrax_recv_buffer {
struct etrax_recv_buffer *next;
unsigned short length;
unsigned char error;
unsigned char pad;
unsigned char buffer[0];
};
struct e100_serial {
struct tty_port port;
int baud;
volatile u8 *ioport; /* R_SERIALx_CTRL */
u32 irq; /* bitnr in R_IRQ_MASK2 for dmaX_descr */
/* Output registers */
volatile u8 *oclrintradr; /* adr to R_DMA_CHx_CLR_INTR */
volatile u32 *ofirstadr; /* adr to R_DMA_CHx_FIRST */
volatile u8 *ocmdadr; /* adr to R_DMA_CHx_CMD */
const volatile u8 *ostatusadr; /* adr to R_DMA_CHx_STATUS */
/* Input registers */
volatile u8 *iclrintradr; /* adr to R_DMA_CHx_CLR_INTR */
volatile u32 *ifirstadr; /* adr to R_DMA_CHx_FIRST */
volatile u8 *icmdadr; /* adr to R_DMA_CHx_CMD */
volatile u32 *idescradr; /* adr to R_DMA_CHx_DESCR */
u8 rx_ctrl; /* shadow for R_SERIALx_REC_CTRL */
u8 tx_ctrl; /* shadow for R_SERIALx_TR_CTRL */
u8 iseteop; /* bit number for R_SET_EOP for the input dma */
int enabled; /* Set to 1 if the port is enabled in HW config */
u8 dma_out_enabled; /* Set to 1 if DMA should be used */
u8 dma_in_enabled; /* Set to 1 if DMA should be used */
/* end of fields defined in rs_table[] in .c-file */
int dma_owner;
unsigned int dma_in_nbr;
unsigned int dma_out_nbr;
unsigned int dma_in_irq_nbr;
unsigned int dma_out_irq_nbr;
unsigned long dma_in_irq_flags;
unsigned long dma_out_irq_flags;
char *dma_in_irq_description;
char *dma_out_irq_description;
enum cris_io_interface io_if;
char *io_if_description;
u8 uses_dma_in; /* Set to 1 if DMA is used */
u8 uses_dma_out; /* Set to 1 if DMA is used */
u8 forced_eop; /* a fifo eop has been forced */
int baud_base; /* For special baudrates */
int custom_divisor; /* For special baudrates */
struct etrax_dma_descr tr_descr;
struct etrax_dma_descr rec_descr[SERIAL_RECV_DESCRIPTORS];
int cur_rec_descr;
volatile int tr_running; /* 1 if output is running */
int x_char; /* xon/xoff character */
unsigned long event;
int line;
int type; /* PORT_ETRAX */
struct circ_buf xmit;
struct etrax_recv_buffer *first_recv_buffer;
struct etrax_recv_buffer *last_recv_buffer;
unsigned int recv_cnt;
unsigned int max_recv_cnt;
struct work_struct work;
struct async_icount icount; /* error-statistics etc.*/
unsigned long char_time_usec; /* The time for 1 char, in usecs */
unsigned long flush_time_usec; /* How often we should flush */
unsigned long last_tx_active_usec; /* Last tx usec in the jiffies */
unsigned long last_tx_active; /* Last tx time in jiffies */
unsigned long last_rx_active_usec; /* Last rx usec in the jiffies */
unsigned long last_rx_active; /* Last rx time in jiffies */
int break_detected_cnt;
int errorcode;
#ifdef CONFIG_ETRAX_RS485
struct serial_rs485 rs485; /* RS-485 support */
#endif
};
/* this PORT is not in the standard serial.h. it's not actually used for
* anything since we only have one type of async serial-port anyway in this
* system.
*/
#define PORT_ETRAX 1
/*
* Events are used to schedule things to happen at timer-interrupt
* time, instead of at rs interrupt time.
*/
#define RS_EVENT_WRITE_WAKEUP 0
#endif /* __KERNEL__ */
#endif /* !_ETRAX_SERIAL_H */

960
drivers/tty/serial/etraxfs-uart.c
View File

@@ -1,960 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/module.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/tty_flip.h>
#include <linux/of.h>
#include <linux/gpio.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <hwregs/ser_defs.h>
#include "serial_mctrl_gpio.h"
#define DRV_NAME "etraxfs-uart"
#define UART_NR CONFIG_ETRAX_SERIAL_PORTS
#define MODIFY_REG(instance, reg, var) \
do { \
if (REG_RD_INT(ser, instance, reg) != \
REG_TYPE_CONV(int, reg_ser_##reg, var)) \
REG_WR(ser, instance, reg, var); \
} while (0)
struct uart_cris_port {
struct uart_port port;
int initialized;
int irq;
void __iomem *regi_ser;
struct mctrl_gpios *gpios;
int write_ongoing;
};
static struct uart_driver etraxfs_uart_driver;
static struct uart_port *console_port;
static int console_baud = 115200;
static struct uart_cris_port *etraxfs_uart_ports[UART_NR];
static void cris_serial_port_init(struct uart_port *port, int line);
static void etraxfs_uart_stop_rx(struct uart_port *port);
static inline void etraxfs_uart_start_tx_bottom(struct uart_port *port);
#ifdef CONFIG_SERIAL_ETRAXFS_CONSOLE
static void
cris_console_write(struct console *co, const char *s, unsigned int count)
{
struct uart_cris_port *up;
int i;
reg_ser_r_stat_din stat;
reg_ser_rw_tr_dma_en tr_dma_en, old;
up = etraxfs_uart_ports[co->index];
if (!up)
return;
/* Switch to manual mode. */
tr_dma_en = old = REG_RD(ser, up->regi_ser, rw_tr_dma_en);
if (tr_dma_en.en == regk_ser_yes) {
tr_dma_en.en = regk_ser_no;
REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en);
}
/* Send data. */
for (i = 0; i < count; i++) {
/* LF -> CRLF */
if (s[i] == '\n') {
do {
stat = REG_RD(ser, up->regi_ser, r_stat_din);
} while (!stat.tr_rdy);
REG_WR_INT(ser, up->regi_ser, rw_dout, '\r');
}
/* Wait until transmitter is ready and send. */
do {
stat = REG_RD(ser, up->regi_ser, r_stat_din);
} while (!stat.tr_rdy);
REG_WR_INT(ser, up->regi_ser, rw_dout, s[i]);
}
/* Restore mode. */
if (tr_dma_en.en != old.en)
REG_WR(ser, up->regi_ser, rw_tr_dma_en, old);
}
static int __init
cris_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (co->index < 0 || co->index >= UART_NR)
co->index = 0;
port = &etraxfs_uart_ports[co->index]->port;
console_port = port;
co->flags |= CON_CONSDEV;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
console_baud = baud;
cris_serial_port_init(port, co->index);
uart_set_options(port, co, baud, parity, bits, flow);
return 0;
}
static struct console cris_console = {
.name = "ttyS",
.write = cris_console_write,
.device = uart_console_device,
.setup = cris_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &etraxfs_uart_driver,
};
#endif /* CONFIG_SERIAL_ETRAXFS_CONSOLE */
static struct uart_driver etraxfs_uart_driver = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
.nr = UART_NR,
#ifdef CONFIG_SERIAL_ETRAXFS_CONSOLE
.cons = &cris_console,
#endif /* CONFIG_SERIAL_ETRAXFS_CONSOLE */
};
static inline int crisv32_serial_get_rts(struct uart_cris_port *up)
{
void __iomem *regi_ser = up->regi_ser;
/*
* Return what the user has controlled rts to or
* what the pin is? (if auto_rts is used it differs during tx)
*/
reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din);
return !(rstat.rts_n == regk_ser_active);
}
/*
* A set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
* 0=0V , 1=3.3V
*/
static inline void crisv32_serial_set_rts(struct uart_cris_port *up,
int set, int force)
{
void __iomem *regi_ser = up->regi_ser;
unsigned long flags;
reg_ser_rw_rec_ctrl rec_ctrl;
local_irq_save(flags);
rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl);
if (set)
rec_ctrl.rts_n = regk_ser_active;
else
rec_ctrl.rts_n = regk_ser_inactive;
REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl);
local_irq_restore(flags);
}
static inline int crisv32_serial_get_cts(struct uart_cris_port *up)
{
void __iomem *regi_ser = up->regi_ser;
reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din);
return (rstat.cts_n == regk_ser_active);
}
/*
* Send a single character for XON/XOFF purposes. We do it in this separate
* function instead of the alternative support port.x_char, in the ...start_tx
* function, so we don't mix up this case with possibly enabling transmission
* of queued-up data (in case that's disabled after *receiving* an XOFF or
* negative CTS). This function is used for both DMA and non-DMA case; see HW
* docs specifically blessing sending characters manually when DMA for
* transmission is enabled and running. We may be asked to transmit despite
* the transmitter being disabled by a ..._stop_tx call so we need to enable
* it temporarily but restore the state afterwards.
*/
static void etraxfs_uart_send_xchar(struct uart_port *port, char ch)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
reg_ser_rw_dout dout = { .data = ch };
reg_ser_rw_ack_intr ack_intr = { .tr_rdy = regk_ser_yes };
reg_ser_r_stat_din rstat;
reg_ser_rw_tr_ctrl prev_tr_ctrl, tr_ctrl;
void __iomem *regi_ser = up->regi_ser;
unsigned long flags;
/*
* Wait for tr_rdy in case a character is already being output. Make
* sure we have integrity between the register reads and the writes
* below, but don't busy-wait with interrupts off and the port lock
* taken.
*/
spin_lock_irqsave(&port->lock, flags);
do {
spin_unlock_irqrestore(&port->lock, flags);
spin_lock_irqsave(&port->lock, flags);
prev_tr_ctrl = tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
rstat = REG_RD(ser, regi_ser, r_stat_din);
} while (!rstat.tr_rdy);
/*
* Ack an interrupt if one was just issued for the previous character
* that was output. This is required for non-DMA as the interrupt is
* used as the only indicator that the transmitter is ready and it
* isn't while this x_char is being transmitted.
*/
REG_WR(ser, regi_ser, rw_ack_intr, ack_intr);
/* Enable the transmitter in case it was disabled. */
tr_ctrl.stop = 0;
REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
/*
* Finally, send the blessed character; nothing should stop it now,
* except for an xoff-detected state, which we'll handle below.
*/
REG_WR(ser, regi_ser, rw_dout, dout);
up->port.icount.tx++;
/* There might be an xoff state to clear. */
rstat = REG_RD(ser, up->regi_ser, r_stat_din);
/*
* Clear any xoff state that *may* have been there to
* inhibit transmission of the character.
*/
if (rstat.xoff_detect) {
reg_ser_rw_xoff_clr xoff_clr = { .clr = 1 };
reg_ser_rw_tr_dma_en tr_dma_en;
REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr);
tr_dma_en = REG_RD(ser, regi_ser, rw_tr_dma_en);
/*
* If we had an xoff state but cleared it, instead sneak in a
* disabled state for the transmitter, after the character we
* sent. Thus we keep the port disabled, just as if the xoff
* state was still in effect (or actually, as if stop_tx had
* been called, as we stop DMA too).
*/
prev_tr_ctrl.stop = 1;
tr_dma_en.en = 0;
REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en);
}
/* Restore "previous" enabled/disabled state of the transmitter. */
REG_WR(ser, regi_ser, rw_tr_ctrl, prev_tr_ctrl);
spin_unlock_irqrestore(&port->lock, flags);
}
/*
* Do not spin_lock_irqsave or disable interrupts by other means here; it's
* already done by the caller.
*/
static void etraxfs_uart_start_tx(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
/* we have already done below if a write is ongoing */
if (up->write_ongoing)
return;
/* Signal that write is ongoing */
up->write_ongoing = 1;
etraxfs_uart_start_tx_bottom(port);
}
static inline void etraxfs_uart_start_tx_bottom(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
void __iomem *regi_ser = up->regi_ser;
reg_ser_rw_tr_ctrl tr_ctrl;
reg_ser_rw_intr_mask intr_mask;
tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
tr_ctrl.stop = regk_ser_no;
REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
intr_mask = REG_RD(ser, regi_ser, rw_intr_mask);
intr_mask.tr_rdy = regk_ser_yes;
REG_WR(ser, regi_ser, rw_intr_mask, intr_mask);
}
/*
* This function handles both the DMA and non-DMA case by ordering the
* transmitter to stop of after the current character. We don't need to wait
* for any such character to be completely transmitted; we do that where it
* matters, like in etraxfs_uart_set_termios. Don't busy-wait here; see
* Documentation/serial/driver: this function is called within
* spin_lock_irq{,save} and thus separate ones would be disastrous (when SMP).
* There's no documented need to set the txd pin to any particular value;
* break setting is controlled solely by etraxfs_uart_break_ctl.
*/
static void etraxfs_uart_stop_tx(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
void __iomem *regi_ser = up->regi_ser;
reg_ser_rw_tr_ctrl tr_ctrl;
reg_ser_rw_intr_mask intr_mask;
reg_ser_rw_tr_dma_en tr_dma_en = {0};
reg_ser_rw_xoff_clr xoff_clr = {0};
/*
* For the non-DMA case, we'd get a tr_rdy interrupt that we're not
* interested in as we're not transmitting any characters. For the
* DMA case, that interrupt is already turned off, but no reason to
* waste code on conditionals here.
*/
intr_mask = REG_RD(ser, regi_ser, rw_intr_mask);
intr_mask.tr_rdy = regk_ser_no;
REG_WR(ser, regi_ser, rw_intr_mask, intr_mask);
tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
tr_ctrl.stop = 1;
REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
/*
* Always clear possible hardware xoff-detected state here, no need to
* unnecessary consider mctrl settings and when they change. We clear
* it here rather than in start_tx: both functions are called as the
* effect of XOFF processing, but start_tx is also called when upper
* levels tell the driver that there are more characters to send, so
* avoid adding code there.
*/
xoff_clr.clr = 1;
REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr);
/*
* Disable transmitter DMA, so that if we're in XON/XOFF, we can send
* those single characters without also giving go-ahead for queued up
* DMA data.
*/
tr_dma_en.en = 0;
REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en);
/*
* Make sure that write_ongoing is reset when stopping tx.
*/
up->write_ongoing = 0;
}
static void etraxfs_uart_stop_rx(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
void __iomem *regi_ser = up->regi_ser;
reg_ser_rw_rec_ctrl rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl);
rec_ctrl.en = regk_ser_no;
REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl);
}
static unsigned int etraxfs_uart_tx_empty(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
unsigned long flags;
unsigned int ret;
reg_ser_r_stat_din rstat = {0};
spin_lock_irqsave(&up->port.lock, flags);
rstat = REG_RD(ser, up->regi_ser, r_stat_din);
ret = rstat.tr_empty ? TIOCSER_TEMT : 0;
spin_unlock_irqrestore(&up->port.lock, flags);
return ret;
}
static unsigned int etraxfs_uart_get_mctrl(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
unsigned int ret;
ret = 0;
if (crisv32_serial_get_rts(up))
ret |= TIOCM_RTS;
if (crisv32_serial_get_cts(up))
ret |= TIOCM_CTS;
return mctrl_gpio_get(up->gpios, &ret);
}
static void etraxfs_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
crisv32_serial_set_rts(up, mctrl & TIOCM_RTS ? 1 : 0, 0);
mctrl_gpio_set(up->gpios, mctrl);
}
static void etraxfs_uart_break_ctl(struct uart_port *port, int break_state)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
unsigned long flags;
reg_ser_rw_tr_ctrl tr_ctrl;
reg_ser_rw_tr_dma_en tr_dma_en;
reg_ser_rw_intr_mask intr_mask;
spin_lock_irqsave(&up->port.lock, flags);
tr_ctrl = REG_RD(ser, up->regi_ser, rw_tr_ctrl);
tr_dma_en = REG_RD(ser, up->regi_ser, rw_tr_dma_en);
intr_mask = REG_RD(ser, up->regi_ser, rw_intr_mask);
if (break_state != 0) { /* Send break */
/*
* We need to disable DMA (if used) or tr_rdy interrupts if no
* DMA. No need to make this conditional on use of DMA;
* disabling will be a no-op for the other mode.
*/
intr_mask.tr_rdy = regk_ser_no;
tr_dma_en.en = 0;
/*
* Stop transmission and set the txd pin to 0 after the
* current character. The txd setting will take effect after
* any current transmission has completed.
*/
tr_ctrl.stop = 1;
tr_ctrl.txd = 0;
} else {
/* Re-enable the serial interrupt. */
intr_mask.tr_rdy = regk_ser_yes;
tr_ctrl.stop = 0;
tr_ctrl.txd = 1;
}
REG_WR(ser, up->regi_ser, rw_tr_ctrl, tr_ctrl);
REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en);
REG_WR(ser, up->regi_ser, rw_intr_mask, intr_mask);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static void
transmit_chars_no_dma(struct uart_cris_port *up)
{
int max_count;
struct circ_buf *xmit = &up->port.state->xmit;
void __iomem *regi_ser = up->regi_ser;
reg_ser_r_stat_din rstat;
reg_ser_rw_ack_intr ack_intr = { .tr_rdy = regk_ser_yes };
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
/* No more to send, so disable the interrupt. */
reg_ser_rw_intr_mask intr_mask;
intr_mask = REG_RD(ser, regi_ser, rw_intr_mask);
intr_mask.tr_rdy = 0;
intr_mask.tr_empty = 0;
REG_WR(ser, regi_ser, rw_intr_mask, intr_mask);
up->write_ongoing = 0;
return;
}
/* If the serport is fast, we send up to max_count bytes before
exiting the loop. */
max_count = 64;
do {
reg_ser_rw_dout dout = { .data = xmit->buf[xmit->tail] };
REG_WR(ser, regi_ser, rw_dout, dout);
REG_WR(ser, regi_ser, rw_ack_intr, ack_intr);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
up->port.icount.tx++;
if (xmit->head == xmit->tail)
break;
rstat = REG_RD(ser, regi_ser, r_stat_din);
} while ((--max_count > 0) && rstat.tr_rdy);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
}
static void receive_chars_no_dma(struct uart_cris_port *up)
{
reg_ser_rs_stat_din stat_din;
reg_ser_r_stat_din rstat;
struct tty_port *port;
struct uart_icount *icount;
int max_count = 16;
char flag;
reg_ser_rw_ack_intr ack_intr = { 0 };
rstat = REG_RD(ser, up->regi_ser, r_stat_din);
icount = &up->port.icount;
port = &up->port.state->port;
do {
stat_din = REG_RD(ser, up->regi_ser, rs_stat_din);
flag = TTY_NORMAL;
ack_intr.dav = 1;
REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr);
icount->rx++;
if (stat_din.framing_err | stat_din.par_err | stat_din.orun) {
if (stat_din.data == 0x00 &&
stat_din.framing_err) {
/* Most likely a break. */
flag = TTY_BREAK;
icount->brk++;
} else if (stat_din.par_err) {
flag = TTY_PARITY;
icount->parity++;
} else if (stat_din.orun) {
flag = TTY_OVERRUN;
icount->overrun++;
} else if (stat_din.framing_err) {
flag = TTY_FRAME;
icount->frame++;
}
}
/*
* If this becomes important, we probably *could* handle this
* gracefully by keeping track of the unhandled character.
*/
if (!tty_insert_flip_char(port, stat_din.data, flag))
panic("%s: No tty buffer space", __func__);
rstat = REG_RD(ser, up->regi_ser, r_stat_din);
} while (rstat.dav && (max_count-- > 0));
spin_unlock(&up->port.lock);
tty_flip_buffer_push(port);
spin_lock(&up->port.lock);
}
static irqreturn_t
ser_interrupt(int irq, void *dev_id)
{
struct uart_cris_port *up = (struct uart_cris_port *)dev_id;
void __iomem *regi_ser;
int handled = 0;
spin_lock(&up->port.lock);
regi_ser = up->regi_ser;
if (regi_ser) {
reg_ser_r_masked_intr masked_intr;
masked_intr = REG_RD(ser, regi_ser, r_masked_intr);
/*
* Check what interrupts are active before taking
* actions. If DMA is used the interrupt shouldn't
* be enabled.
*/
if (masked_intr.dav) {
receive_chars_no_dma(up);
handled = 1;
}
if (masked_intr.tr_rdy) {
transmit_chars_no_dma(up);
handled = 1;
}
}
spin_unlock(&up->port.lock);
return IRQ_RETVAL(handled);
}
#ifdef CONFIG_CONSOLE_POLL
static int etraxfs_uart_get_poll_char(struct uart_port *port)
{
reg_ser_rs_stat_din stat;
reg_ser_rw_ack_intr ack_intr = { 0 };
struct uart_cris_port *up = (struct uart_cris_port *)port;
do {
stat = REG_RD(ser, up->regi_ser, rs_stat_din);
} while (!stat.dav);
/* Ack the data_avail interrupt. */
ack_intr.dav = 1;
REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr);
return stat.data;
}
static void etraxfs_uart_put_poll_char(struct uart_port *port,
unsigned char c)
{
reg_ser_r_stat_din stat;
struct uart_cris_port *up = (struct uart_cris_port *)port;
do {
stat = REG_RD(ser, up->regi_ser, r_stat_din);
} while (!stat.tr_rdy);
REG_WR_INT(ser, up->regi_ser, rw_dout, c);
}
#endif /* CONFIG_CONSOLE_POLL */
static int etraxfs_uart_startup(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
unsigned long flags;
reg_ser_rw_intr_mask ser_intr_mask = {0};
ser_intr_mask.dav = regk_ser_yes;
if (request_irq(etraxfs_uart_ports[port->line]->irq, ser_interrupt,
0, DRV_NAME, etraxfs_uart_ports[port->line]))
panic("irq ser%d", port->line);
spin_lock_irqsave(&up->port.lock, flags);
REG_WR(ser, up->regi_ser, rw_intr_mask, ser_intr_mask);
etraxfs_uart_set_mctrl(&up->port, up->port.mctrl);
spin_unlock_irqrestore(&up->port.lock, flags);
return 0;
}
static void etraxfs_uart_shutdown(struct uart_port *port)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
etraxfs_uart_stop_tx(port);
etraxfs_uart_stop_rx(port);
free_irq(etraxfs_uart_ports[port->line]->irq,
etraxfs_uart_ports[port->line]);
etraxfs_uart_set_mctrl(&up->port, up->port.mctrl);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static void
etraxfs_uart_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
unsigned long flags;
reg_ser_rw_xoff xoff;
reg_ser_rw_xoff_clr xoff_clr = {0};
reg_ser_rw_tr_ctrl tx_ctrl = {0};
reg_ser_rw_tr_dma_en tx_dma_en = {0};
reg_ser_rw_rec_ctrl rx_ctrl = {0};
reg_ser_rw_tr_baud_div tx_baud_div = {0};
reg_ser_rw_rec_baud_div rx_baud_div = {0};
int baud;
if (old &&
termios->c_cflag == old->c_cflag &&
termios->c_iflag == old->c_iflag)
return;
/* Tx: 8 bit, no/even parity, 1 stop bit, no cts. */
tx_ctrl.base_freq = regk_ser_f29_493;
tx_ctrl.en = 0;
tx_ctrl.stop = 0;
tx_ctrl.auto_rts = regk_ser_no;
tx_ctrl.txd = 1;
tx_ctrl.auto_cts = 0;
/* Rx: 8 bit, no/even parity. */
rx_ctrl.dma_err = regk_ser_stop;
rx_ctrl.sampling = regk_ser_majority;
rx_ctrl.timeout = 1;
rx_ctrl.rts_n = regk_ser_inactive;
/* Common for tx and rx: 8N1. */
tx_ctrl.data_bits = regk_ser_bits8;
rx_ctrl.data_bits = regk_ser_bits8;
tx_ctrl.par = regk_ser_even;
rx_ctrl.par = regk_ser_even;
tx_ctrl.par_en = regk_ser_no;
rx_ctrl.par_en = regk_ser_no;
tx_ctrl.stop_bits = regk_ser_bits1;
/*
* Change baud-rate and write it to the hardware.
*
* baud_clock = base_freq / (divisor*8)
* divisor = base_freq / (baud_clock * 8)
* base_freq is either:
* off, ext, 29.493MHz, 32.000 MHz, 32.768 MHz or 100 MHz
* 20.493MHz is used for standard baudrates
*/
/*
* For the console port we keep the original baudrate here. Not very
* beautiful.
*/
if ((port != console_port) || old)
baud = uart_get_baud_rate(port, termios, old, 0,
port->uartclk / 8);
else
baud = console_baud;
tx_baud_div.div = 29493000 / (8 * baud);
/* Rx uses same as tx. */
rx_baud_div.div = tx_baud_div.div;
rx_ctrl.base_freq = tx_ctrl.base_freq;
if ((termios->c_cflag & CSIZE) == CS7) {
/* Set 7 bit mode. */
tx_ctrl.data_bits = regk_ser_bits7;
rx_ctrl.data_bits = regk_ser_bits7;
}
if (termios->c_cflag & CSTOPB) {
/* Set 2 stop bit mode. */
tx_ctrl.stop_bits = regk_ser_bits2;
}
if (termios->c_cflag & PARENB) {
/* Enable parity. */
tx_ctrl.par_en = regk_ser_yes;
rx_ctrl.par_en = regk_ser_yes;
}
if (termios->c_cflag & CMSPAR) {
if (termios->c_cflag & PARODD) {
/* Set mark parity if PARODD and CMSPAR. */
tx_ctrl.par = regk_ser_mark;
rx_ctrl.par = regk_ser_mark;
} else {
tx_ctrl.par = regk_ser_space;
rx_ctrl.par = regk_ser_space;
}
} else {
if (termios->c_cflag & PARODD) {
/* Set odd parity. */
tx_ctrl.par = regk_ser_odd;
rx_ctrl.par = regk_ser_odd;
}
}
if (termios->c_cflag & CRTSCTS) {
/* Enable automatic CTS handling. */
tx_ctrl.auto_cts = regk_ser_yes;
}
/* Make sure the tx and rx are enabled. */
tx_ctrl.en = regk_ser_yes;
rx_ctrl.en = regk_ser_yes;
spin_lock_irqsave(&port->lock, flags);
tx_dma_en.en = 0;
REG_WR(ser, up->regi_ser, rw_tr_dma_en, tx_dma_en);
/* Actually write the control regs (if modified) to the hardware. */
uart_update_timeout(port, termios->c_cflag, port->uartclk/8);
MODIFY_REG(up->regi_ser, rw_rec_baud_div, rx_baud_div);
MODIFY_REG(up->regi_ser, rw_rec_ctrl, rx_ctrl);
MODIFY_REG(up->regi_ser, rw_tr_baud_div, tx_baud_div);
MODIFY_REG(up->regi_ser, rw_tr_ctrl, tx_ctrl);
tx_dma_en.en = 0;
REG_WR(ser, up->regi_ser, rw_tr_dma_en, tx_dma_en);
xoff = REG_RD(ser, up->regi_ser, rw_xoff);
if (up->port.state && up->port.state->port.tty &&
(up->port.state->port.tty->termios.c_iflag & IXON)) {
xoff.chr = STOP_CHAR(up->port.state->port.tty);
xoff.automatic = regk_ser_yes;
} else
xoff.automatic = regk_ser_no;
MODIFY_REG(up->regi_ser, rw_xoff, xoff);
/*
* Make sure we don't start in an automatically shut-off state due to
* a previous early exit.
*/
xoff_clr.clr = 1;
REG_WR(ser, up->regi_ser, rw_xoff_clr, xoff_clr);
etraxfs_uart_set_mctrl(&up->port, up->port.mctrl);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static const char *
etraxfs_uart_type(struct uart_port *port)
{
return "CRISv32";
}
static void etraxfs_uart_release_port(struct uart_port *port)
{
}
static int etraxfs_uart_request_port(struct uart_port *port)
{
return 0;
}
static void etraxfs_uart_config_port(struct uart_port *port, int flags)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
up->port.type = PORT_CRIS;
}
static const struct uart_ops etraxfs_uart_pops = {
.tx_empty = etraxfs_uart_tx_empty,
.set_mctrl = etraxfs_uart_set_mctrl,
.get_mctrl = etraxfs_uart_get_mctrl,
.stop_tx = etraxfs_uart_stop_tx,
.start_tx = etraxfs_uart_start_tx,
.send_xchar = etraxfs_uart_send_xchar,
.stop_rx = etraxfs_uart_stop_rx,
.break_ctl = etraxfs_uart_break_ctl,
.startup = etraxfs_uart_startup,
.shutdown = etraxfs_uart_shutdown,
.set_termios = etraxfs_uart_set_termios,
.type = etraxfs_uart_type,
.release_port = etraxfs_uart_release_port,
.request_port = etraxfs_uart_request_port,
.config_port = etraxfs_uart_config_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = etraxfs_uart_get_poll_char,
.poll_put_char = etraxfs_uart_put_poll_char,
#endif
};
static void cris_serial_port_init(struct uart_port *port, int line)
{
struct uart_cris_port *up = (struct uart_cris_port *)port;
if (up->initialized)
return;
up->initialized = 1;
port->line = line;
spin_lock_init(&port->lock);
port->ops = &etraxfs_uart_pops;
port->irq = up->irq;
port->iobase = (unsigned long) up->regi_ser;
port->uartclk = 29493000;
/*
* We can't fit any more than 255 here (unsigned char), though
* actually UART_XMIT_SIZE characters could be pending output.
* At time of this writing, the definition of "fifosize" is here the
* amount of characters that can be pending output after a start_tx call
* until tx_empty returns 1: see serial_core.c:uart_wait_until_sent.
* This matters for timeout calculations unfortunately, but keeping
* larger amounts at the DMA wouldn't win much so let's just play nice.
*/
port->fifosize = 255;
port->flags = UPF_BOOT_AUTOCONF;
}
static int etraxfs_uart_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct uart_cris_port *up;
int dev_id;
if (!np)
return -ENODEV;
dev_id = of_alias_get_id(np, "serial");
if (dev_id < 0)
dev_id = 0;
if (dev_id >= UART_NR)
return -EINVAL;
if (etraxfs_uart_ports[dev_id])
return -EBUSY;
up = devm_kzalloc(&pdev->dev, sizeof(struct uart_cris_port),
GFP_KERNEL);
if (!up)
return -ENOMEM;
up->irq = irq_of_parse_and_map(np, 0);
up->regi_ser = of_iomap(np, 0);
up->port.dev = &pdev->dev;
up->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0);
if (IS_ERR(up->gpios))
return PTR_ERR(up->gpios);
cris_serial_port_init(&up->port, dev_id);
etraxfs_uart_ports[dev_id] = up;
platform_set_drvdata(pdev, &up->port);
uart_add_one_port(&etraxfs_uart_driver, &up->port);
return 0;
}
static int etraxfs_uart_remove(struct platform_device *pdev)
{
struct uart_port *port;
port = platform_get_drvdata(pdev);
uart_remove_one_port(&etraxfs_uart_driver, port);
etraxfs_uart_ports[port->line] = NULL;
return 0;
}
static const struct of_device_id etraxfs_uart_dt_ids[] = {
{ .compatible = "axis,etraxfs-uart" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, etraxfs_uart_dt_ids);
static struct platform_driver etraxfs_uart_platform_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(etraxfs_uart_dt_ids),
},
.probe = etraxfs_uart_probe,
.remove = etraxfs_uart_remove,
};
static int __init etraxfs_uart_init(void)
{
int ret;
ret = uart_register_driver(&etraxfs_uart_driver);
if (ret)
return ret;
ret = platform_driver_register(&etraxfs_uart_platform_driver);
if (ret)
uart_unregister_driver(&etraxfs_uart_driver);
return ret;
}
static void __exit etraxfs_uart_exit(void)
{
platform_driver_unregister(&etraxfs_uart_platform_driver);
uart_unregister_driver(&etraxfs_uart_driver);
}
module_init(etraxfs_uart_init);
module_exit(etraxfs_uart_exit);

1053
drivers/tty/serial/m32r_sio.c
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File diff suppressed because it is too large Load Diff

150
drivers/tty/serial/m32r_sio_reg.h
View File

@@ -1,150 +0,0 @@
// SPDX-License-Identifier: GPL-1.0+
/*
* m32r_sio_reg.h
*
* Copyright (C) 1992, 1994 by Theodore Ts'o.
* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
*
* These are the UART port assignments, expressed as offsets from the base
* register. These assignments should hold for any serial port based on
* a 8250, 16450, or 16550(A).
*/
#ifndef _M32R_SIO_REG_H
#define _M32R_SIO_REG_H
#ifdef CONFIG_SERIAL_M32R_PLDSIO
#define SIOCR 0x000
#define SIOMOD0 0x002
#define SIOMOD1 0x004
#define SIOSTS 0x006
#define SIOTRCR 0x008
#define SIOBAUR 0x00a
// #define SIORBAUR 0x018
#define SIOTXB 0x00c
#define SIORXB 0x00e
#define UART_RX ((unsigned long) PLD_ESIO0RXB)
/* In: Receive buffer (DLAB=0) */
#define UART_TX ((unsigned long) PLD_ESIO0TXB)
/* Out: Transmit buffer (DLAB=0) */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
* In: Fifo count
* Out: Fifo custom trigger levels
* XR16C85x only */
#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
#define UART_IER ((unsigned long) PLD_ESIO0INTCR)
/* Out: Interrupt Enable Register */
#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
* XR16C85x only */
#define UART_IIR 0 /* In: Interrupt ID Register */
#define UART_FCR 0 /* Out: FIFO Control Register */
#define UART_EFR 0 /* I/O: Extended Features Register */
/* (DLAB=1, 16C660 only) */
#define UART_LCR 0 /* Out: Line Control Register */
#define UART_MCR 0 /* Out: Modem Control Register */
#define UART_LSR ((unsigned long) PLD_ESIO0STS)
/* In: Line Status Register */
#define UART_MSR 0 /* In: Modem Status Register */
#define UART_SCR 0 /* I/O: Scratch Register */
#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
* FCTR bit 6 selects SCR or EMSR
* XR16c85x only */
#else /* not CONFIG_SERIAL_M32R_PLDSIO */
#define SIOCR 0x000
#define SIOMOD0 0x004
#define SIOMOD1 0x008
#define SIOSTS 0x00c
#define SIOTRCR 0x010
#define SIOBAUR 0x014
#define SIORBAUR 0x018
#define SIOTXB 0x01c
#define SIORXB 0x020
#define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
#define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
* In: Fifo count
* Out: Fifo custom trigger levels
* XR16C85x only */
#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
#define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
* XR16C85x only */
#define UART_IIR 0 /* In: Interrupt ID Register */
#define UART_FCR 0 /* Out: FIFO Control Register */
#define UART_EFR 0 /* I/O: Extended Features Register */
/* (DLAB=1, 16C660 only) */
#define UART_LCR 0 /* Out: Line Control Register */
#define UART_MCR 0 /* Out: Modem Control Register */
#define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */
#define UART_MSR 0 /* In: Modem Status Register */
#define UART_SCR 0 /* I/O: Scratch Register */
#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
* FCTR bit 6 selects SCR or EMSR
* XR16c85x only */
#endif /* CONFIG_SERIAL_M32R_PLDSIO */
#define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
/*
* These are the definitions for the Line Control Register
*
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_LCR_SBC 0x40 /* Set break control */
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
#define UART_LCR_EPAR 0x10 /* Even parity select */
#define UART_LCR_PARITY 0x08 /* Parity Enable */
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_TEMT 0x02 /* Transmitter empty */
#define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x00 /* Break interrupt indicator */
#define UART_LSR_FE 0x80 /* Frame error indicator */
#define UART_LSR_PE 0x40 /* Parity error indicator */
#define UART_LSR_OE 0x20 /* Overrun error indicator */
#define UART_LSR_DR 0x04 /* Receiver data ready */
/*
* These are the definitions for the Interrupt Identification Register
*/
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
/*
* These are the definitions for the Interrupt Enable Register
*/
#define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
#endif /* _M32R_SIO_REG_H */

689
drivers/tty/serial/tilegx.c
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@@ -1,689 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2013 Tilera Corporation. All Rights Reserved.
*
* TILEGx UART driver.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <gxio/common.h>
#include <gxio/iorpc_globals.h>
#include <gxio/iorpc_uart.h>
#include <gxio/kiorpc.h>
#include <hv/drv_uart_intf.h>
/*
* Use device name ttyS, major 4, minor 64-65.
* This is the usual serial port name, 8250 conventional range.
*/
#define TILEGX_UART_MAJOR TTY_MAJOR
#define TILEGX_UART_MINOR 64
#define TILEGX_UART_NAME "ttyS"
#define DRIVER_NAME_STRING "TILEGx_Serial"
#define TILEGX_UART_REF_CLK 125000000; /* REF_CLK is always 125 MHz. */
struct tile_uart_port {
/* UART port. */
struct uart_port uart;
/* GXIO device context. */
gxio_uart_context_t context;
/* UART access mutex. */
struct mutex mutex;
/* CPU receiving interrupts. */
int irq_cpu;
};
static struct tile_uart_port tile_uart_ports[TILEGX_UART_NR];
static struct uart_driver tilegx_uart_driver;
/*
* Read UART rx fifo, and insert the chars into tty buffer.
*/
static void receive_chars(struct tile_uart_port *tile_uart,
struct tty_struct *tty)
{
int i;
char c;
UART_FIFO_COUNT_t count;
gxio_uart_context_t *context = &tile_uart->context;
struct tty_port *port = tty->port;
count.word = gxio_uart_read(context, UART_FIFO_COUNT);
for (i = 0; i < count.rfifo_count; i++) {
c = (char)gxio_uart_read(context, UART_RECEIVE_DATA);
tty_insert_flip_char(port, c, TTY_NORMAL);
}
}
/*
* Drain the Rx FIFO, called by interrupt handler.
*/
static void handle_receive(struct tile_uart_port *tile_uart)
{
struct tty_port *port = &tile_uart->uart.state->port;
struct tty_struct *tty = tty_port_tty_get(port);
gxio_uart_context_t *context = &tile_uart->context;
if (!tty)
return;
/* First read UART rx fifo. */
receive_chars(tile_uart, tty);
/* Reset RFIFO_WE interrupt. */
gxio_uart_write(context, UART_INTERRUPT_STATUS,
UART_INTERRUPT_MASK__RFIFO_WE_MASK);
/* Final read, if any chars comes between the first read and
* the interrupt reset.
*/
receive_chars(tile_uart, tty);
spin_unlock(&tile_uart->uart.lock);
tty_flip_buffer_push(port);
spin_lock(&tile_uart->uart.lock);
tty_kref_put(tty);
}
/*
* Push one char to UART Write FIFO.
* Return 0 on success, -1 if write filo is full.
*/
static int tilegx_putchar(gxio_uart_context_t *context, char c)
{
UART_FLAG_t flag;
flag.word = gxio_uart_read(context, UART_FLAG);
if (flag.wfifo_full)
return -1;
gxio_uart_write(context, UART_TRANSMIT_DATA, (unsigned long)c);
return 0;
}
/*
* Send chars to UART Write FIFO; called by interrupt handler.
*/
static void handle_transmit(struct tile_uart_port *tile_uart)
{
unsigned char ch;
struct uart_port *port;
struct circ_buf *xmit;
gxio_uart_context_t *context = &tile_uart->context;
/* First reset WFIFO_RE interrupt. */
gxio_uart_write(context, UART_INTERRUPT_STATUS,
UART_INTERRUPT_MASK__WFIFO_RE_MASK);
port = &tile_uart->uart;
xmit = &port->state->xmit;
if (port->x_char) {
if (tilegx_putchar(context, port->x_char))
return;
port->x_char = 0;
port->icount.tx++;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
return;
while (!uart_circ_empty(xmit)) {
ch = xmit->buf[xmit->tail];
if (tilegx_putchar(context, ch))
break;
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
/* Reset WFIFO_RE interrupt. */
gxio_uart_write(context, UART_INTERRUPT_STATUS,
UART_INTERRUPT_MASK__WFIFO_RE_MASK);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
/*
* UART Interrupt handler.
*/
static irqreturn_t tilegx_interrupt(int irq, void *dev_id)
{
unsigned long flags;
UART_INTERRUPT_STATUS_t intr_stat;
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
struct uart_port *port = dev_id;
irqreturn_t ret = IRQ_NONE;
spin_lock_irqsave(&port->lock, flags);
tile_uart = container_of(port, struct tile_uart_port, uart);
context = &tile_uart->context;
intr_stat.word = gxio_uart_read(context, UART_INTERRUPT_STATUS);
if (intr_stat.rfifo_we) {
handle_receive(tile_uart);
ret = IRQ_HANDLED;
}
if (intr_stat.wfifo_re) {
handle_transmit(tile_uart);
ret = IRQ_HANDLED;
}
spin_unlock_irqrestore(&port->lock, flags);
return ret;
}
/*
* Return TIOCSER_TEMT when transmitter FIFO is empty.
*/
static u_int tilegx_tx_empty(struct uart_port *port)
{
int ret;
UART_FLAG_t flag;
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
tile_uart = container_of(port, struct tile_uart_port, uart);
if (!mutex_trylock(&tile_uart->mutex))
return 0;
context = &tile_uart->context;
flag.word = gxio_uart_read(context, UART_FLAG);
ret = (flag.wfifo_empty) ? TIOCSER_TEMT : 0;
mutex_unlock(&tile_uart->mutex);
return ret;
}
/*
* Set state of the modem control output lines.
*/
static void tilegx_set_mctrl(struct uart_port *port, u_int mctrl)
{
/* N/A */
}
/*
* Get state of the modem control input lines.
*/
static u_int tilegx_get_mctrl(struct uart_port *port)
{
return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}
/*
* Stop transmitting.
*/
static void tilegx_stop_tx(struct uart_port *port)
{
/* N/A */
}
/*
* Start transmitting.
*/
static void tilegx_start_tx(struct uart_port *port)
{
unsigned char ch;
struct circ_buf *xmit;
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
tile_uart = container_of(port, struct tile_uart_port, uart);
if (!mutex_trylock(&tile_uart->mutex))
return;
context = &tile_uart->context;
xmit = &port->state->xmit;
if (port->x_char) {
if (tilegx_putchar(context, port->x_char))
return;
port->x_char = 0;
port->icount.tx++;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
mutex_unlock(&tile_uart->mutex);
return;
}
while (!uart_circ_empty(xmit)) {
ch = xmit->buf[xmit->tail];
if (tilegx_putchar(context, ch))
break;
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
port->icount.tx++;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
mutex_unlock(&tile_uart->mutex);
}
/*
* Stop receiving - port is in process of being closed.
*/
static void tilegx_stop_rx(struct uart_port *port)
{
int err;
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
int cpu;
tile_uart = container_of(port, struct tile_uart_port, uart);
if (!mutex_trylock(&tile_uart->mutex))
return;
context = &tile_uart->context;
cpu = tile_uart->irq_cpu;
err = gxio_uart_cfg_interrupt(context, cpu_x(cpu), cpu_y(cpu),
KERNEL_PL, -1);
mutex_unlock(&tile_uart->mutex);
}
/*
* Control the transmission of a break signal.
*/
static void tilegx_break_ctl(struct uart_port *port, int break_state)
{
/* N/A */
}
/*
* Perform initialization and enable port for reception.
*/
static int tilegx_startup(struct uart_port *port)
{
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
int ret = 0;
int cpu = raw_smp_processor_id(); /* pick an arbitrary cpu */
tile_uart = container_of(port, struct tile_uart_port, uart);
if (mutex_lock_interruptible(&tile_uart->mutex))
return -EBUSY;
context = &tile_uart->context;
/* Now open the hypervisor device if we haven't already. */
if (context->fd < 0) {
UART_INTERRUPT_MASK_t intr_mask;
/* Initialize UART device. */
ret = gxio_uart_init(context, port->line);
if (ret) {
ret = -ENXIO;
goto err;
}
/* Create our IRQs. */
port->irq = irq_alloc_hwirq(-1);
if (!port->irq)
goto err_uart_dest;
tile_irq_activate(port->irq, TILE_IRQ_PERCPU);
/* Register our IRQs. */
ret = request_irq(port->irq, tilegx_interrupt, 0,
tilegx_uart_driver.driver_name, port);
if (ret)
goto err_dest_irq;
/* Request that the hardware start sending us interrupts. */
tile_uart->irq_cpu = cpu;
ret = gxio_uart_cfg_interrupt(context, cpu_x(cpu), cpu_y(cpu),
KERNEL_PL, port->irq);
if (ret)
goto err_free_irq;
/* Enable UART Tx/Rx Interrupt. */
intr_mask.word = gxio_uart_read(context, UART_INTERRUPT_MASK);
intr_mask.wfifo_re = 0;
intr_mask.rfifo_we = 0;
gxio_uart_write(context, UART_INTERRUPT_MASK, intr_mask.word);
/* Reset the Tx/Rx interrupt in case it's set. */
gxio_uart_write(context, UART_INTERRUPT_STATUS,
UART_INTERRUPT_MASK__WFIFO_RE_MASK |
UART_INTERRUPT_MASK__RFIFO_WE_MASK);
}
mutex_unlock(&tile_uart->mutex);
return ret;
err_free_irq:
free_irq(port->irq, port);
err_dest_irq:
irq_free_hwirq(port->irq);
err_uart_dest:
gxio_uart_destroy(context);
ret = -ENXIO;
err:
mutex_unlock(&tile_uart->mutex);
return ret;
}
/*
* Release kernel resources if it is the last close, disable the port,
* free IRQ and close the port.
*/
static void tilegx_shutdown(struct uart_port *port)
{
int err;
UART_INTERRUPT_MASK_t intr_mask;
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
int cpu;
tile_uart = container_of(port, struct tile_uart_port, uart);
if (mutex_lock_interruptible(&tile_uart->mutex))
return;
context = &tile_uart->context;
/* Disable UART Tx/Rx Interrupt. */
intr_mask.word = gxio_uart_read(context, UART_INTERRUPT_MASK);
intr_mask.wfifo_re = 1;
intr_mask.rfifo_we = 1;
gxio_uart_write(context, UART_INTERRUPT_MASK, intr_mask.word);
/* Request that the hardware stop sending us interrupts. */
cpu = tile_uart->irq_cpu;
err = gxio_uart_cfg_interrupt(context, cpu_x(cpu), cpu_y(cpu),
KERNEL_PL, -1);
if (port->irq > 0) {
free_irq(port->irq, port);
irq_free_hwirq(port->irq);
port->irq = 0;
}
gxio_uart_destroy(context);
mutex_unlock(&tile_uart->mutex);
}
/*
* Flush the buffer.
*/
static void tilegx_flush_buffer(struct uart_port *port)
{
/* N/A */
}
/*
* Change the port parameters.
*/
static void tilegx_set_termios(struct uart_port *port,
struct ktermios *termios, struct ktermios *old)
{
int err;
UART_DIVISOR_t divisor;
UART_TYPE_t type;
unsigned int baud;
struct tile_uart_port *tile_uart;
gxio_uart_context_t *context;
tile_uart = container_of(port, struct tile_uart_port, uart);
if (!mutex_trylock(&tile_uart->mutex))
return;
context = &tile_uart->context;
/* Open the hypervisor device if we haven't already. */
if (context->fd < 0) {
err = gxio_uart_init(context, port->line);
if (err) {
mutex_unlock(&tile_uart->mutex);
return;
}
}
divisor.word = gxio_uart_read(context, UART_DIVISOR);
type.word = gxio_uart_read(context, UART_TYPE);
/* Divisor. */
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
divisor.divisor = uart_get_divisor(port, baud);
/* Byte size. */
if ((termios->c_cflag & CSIZE) == CS7)
type.dbits = UART_TYPE__DBITS_VAL_SEVEN_DBITS;
else
type.dbits = UART_TYPE__DBITS_VAL_EIGHT_DBITS;
/* Parity. */
if (termios->c_cflag & PARENB) {
/* Mark or Space parity. */
if (termios->c_cflag & CMSPAR)
if (termios->c_cflag & PARODD)
type.ptype = UART_TYPE__PTYPE_VAL_MARK;
else
type.ptype = UART_TYPE__PTYPE_VAL_SPACE;
else if (termios->c_cflag & PARODD)
type.ptype = UART_TYPE__PTYPE_VAL_ODD;
else
type.ptype = UART_TYPE__PTYPE_VAL_EVEN;
} else
type.ptype = UART_TYPE__PTYPE_VAL_NONE;
/* Stop bits. */
if (termios->c_cflag & CSTOPB)
type.sbits = UART_TYPE__SBITS_VAL_TWO_SBITS;
else
type.sbits = UART_TYPE__SBITS_VAL_ONE_SBITS;
/* Set the uart paramters. */
gxio_uart_write(context, UART_DIVISOR, divisor.word);
gxio_uart_write(context, UART_TYPE, type.word);
mutex_unlock(&tile_uart->mutex);
}
/*
* Return string describing the specified port.
*/
static const char *tilegx_type(struct uart_port *port)
{
return port->type == PORT_TILEGX ? DRIVER_NAME_STRING : NULL;
}
/*
* Release the resources being used by 'port'.
*/
static void tilegx_release_port(struct uart_port *port)
{
/* Nothing to release. */
}
/*
* Request the resources being used by 'port'.
*/
static int tilegx_request_port(struct uart_port *port)
{
/* Always present. */
return 0;
}
/*
* Configure/autoconfigure the port.
*/
static void tilegx_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_TILEGX;
}
/*
* Verify the new serial_struct (for TIOCSSERIAL).
*/
static int tilegx_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_TILEGX))
return -EINVAL;
return 0;
}
#ifdef CONFIG_CONSOLE_POLL
/*
* Console polling routines for writing and reading from the uart while
* in an interrupt or debug context.
*/
static int tilegx_poll_get_char(struct uart_port *port)
{
UART_FIFO_COUNT_t count;
gxio_uart_context_t *context;
struct tile_uart_port *tile_uart;
tile_uart = container_of(port, struct tile_uart_port, uart);
context = &tile_uart->context;
count.word = gxio_uart_read(context, UART_FIFO_COUNT);
if (count.rfifo_count == 0)
return NO_POLL_CHAR;
return (char)gxio_uart_read(context, UART_RECEIVE_DATA);
}
static void tilegx_poll_put_char(struct uart_port *port, unsigned char c)
{
gxio_uart_context_t *context;
struct tile_uart_port *tile_uart;
tile_uart = container_of(port, struct tile_uart_port, uart);
context = &tile_uart->context;
gxio_uart_write(context, UART_TRANSMIT_DATA, (unsigned long)c);
}
#endif /* CONFIG_CONSOLE_POLL */
static const struct uart_ops tilegx_ops = {
.tx_empty = tilegx_tx_empty,
.set_mctrl = tilegx_set_mctrl,
.get_mctrl = tilegx_get_mctrl,
.stop_tx = tilegx_stop_tx,
.start_tx = tilegx_start_tx,
.stop_rx = tilegx_stop_rx,
.break_ctl = tilegx_break_ctl,
.startup = tilegx_startup,
.shutdown = tilegx_shutdown,
.flush_buffer = tilegx_flush_buffer,
.set_termios = tilegx_set_termios,
.type = tilegx_type,
.release_port = tilegx_release_port,
.request_port = tilegx_request_port,
.config_port = tilegx_config_port,
.verify_port = tilegx_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = tilegx_poll_get_char,
.poll_put_char = tilegx_poll_put_char,
#endif
};
static void tilegx_init_ports(void)
{
int i;
struct uart_port *port;
for (i = 0; i < TILEGX_UART_NR; i++) {
port = &tile_uart_ports[i].uart;
port->ops = &tilegx_ops;
port->line = i;
port->type = PORT_TILEGX;
port->uartclk = TILEGX_UART_REF_CLK;
port->flags = UPF_BOOT_AUTOCONF;
tile_uart_ports[i].context.fd = -1;
mutex_init(&tile_uart_ports[i].mutex);
}
}
static struct uart_driver tilegx_uart_driver = {
.owner = THIS_MODULE,
.driver_name = DRIVER_NAME_STRING,
.dev_name = TILEGX_UART_NAME,
.major = TILEGX_UART_MAJOR,
.minor = TILEGX_UART_MINOR,
.nr = TILEGX_UART_NR,
};
static int __init tilegx_init(void)
{
int i;
int ret;
struct tty_driver *tty_drv;
ret = uart_register_driver(&tilegx_uart_driver);
if (ret)
return ret;
tty_drv = tilegx_uart_driver.tty_driver;
tty_drv->init_termios.c_cflag = B115200 | CS8 | CREAD | HUPCL | CLOCAL;
tty_drv->init_termios.c_ispeed = 115200;
tty_drv->init_termios.c_ospeed = 115200;
tilegx_init_ports();
for (i = 0; i < TILEGX_UART_NR; i++) {
struct uart_port *port = &tile_uart_ports[i].uart;
ret = uart_add_one_port(&tilegx_uart_driver, port);
}
return 0;
}
static void __exit tilegx_exit(void)
{
int i;
struct uart_port *port;
for (i = 0; i < TILEGX_UART_NR; i++) {
port = &tile_uart_ports[i].uart;
uart_remove_one_port(&tilegx_uart_driver, port);
}
uart_unregister_driver(&tilegx_uart_driver);
}
module_init(tilegx_init);
module_exit(tilegx_exit);
MODULE_AUTHOR("Tilera Corporation");
MODULE_DESCRIPTION("TILEGx serial port driver");
MODULE_LICENSE("GPL");