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drm/amd/powerplay: correct power reading on fiji

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Set sampling period as 500ms to provide a smooth power
reading output. Also, correct the register for power
reading.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Evan Quan
2019-02-25 16:44:36 +08:00
committed by Alex Deucher
parent 8f2bf88411
commit f5742ec364
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@@ -3491,14 +3491,14 @@ static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_PM_STATUS_94, 0); ixSMU_PM_STATUS_95, 0);
for (i = 0; i < 10; i++) { for (i = 0; i < 10; i++) {
mdelay(1); mdelay(500);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample); smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
tmp = cgs_read_ind_register(hwmgr->device, tmp = cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, CGS_IND_REG__SMC,
ixSMU_PM_STATUS_94); ixSMU_PM_STATUS_95);
if (tmp != 0) if (tmp != 0)
break; break;
} }