Merge tag 'char-misc-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc updates from Greg KH: "Here is the "big" char/misc driver patchset for 4.13-rc1. Lots of stuff in here, a large thunderbolt update, w1 driver header reorg, the new mux driver subsystem, google firmware driver updates, and a raft of other smaller things. Full details in the shortlog. All of these have been in linux-next for a while with the only reported issue being a merge problem with this tree and the jc-docs tree in the w1 documentation area" * tag 'char-misc-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (147 commits) misc: apds990x: Use sysfs_match_string() helper mei: drop unreachable code in mei_start mei: validate the message header only in first fragment. DocBook: w1: Update W1 file locations and names in DocBook mux: adg792a: always require I2C support nvmem: rockchip-efuse: add support for rk322x-efuse nvmem: core: add locking to nvmem_find_cell nvmem: core: Call put_device() in nvmem_unregister() nvmem: core: fix leaks on registration errors nvmem: correct Broadcom OTP controller driver writes w1: Add subsystem kernel public interface drivers/fsi: Add module license to core driver drivers/fsi: Use asynchronous slave mode drivers/fsi: Add hub master support drivers/fsi: Add SCOM FSI client device driver drivers/fsi/gpio: Add tracepoints for GPIO master drivers/fsi: Add GPIO based FSI master drivers/fsi: Document FSI master sysfs files in ABI drivers/fsi: Add error handling for slave drivers/fsi: Add tracepoints for low-level operations ...
This commit is contained in:
Linus Torvalds
@@ -89,4 +89,18 @@ config CORESIGHT_STM
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logging useful software events or data coming from various entities
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in the system, possibly running different OSs
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config CORESIGHT_CPU_DEBUG
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tristate "CoreSight CPU Debug driver"
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depends on ARM || ARM64
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depends on DEBUG_FS
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help
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This driver provides support for coresight debugging module. This
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is primarily used to dump sample-based profiling registers when
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system triggers panic, the driver will parse context registers so
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can quickly get to know program counter (PC), secure state,
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exception level, etc. Before use debugging functionality, platform
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needs to ensure the clock domain and power domain are enabled
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properly, please refer Documentation/trace/coresight-cpu-debug.txt
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for detailed description and the example for usage.
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endif
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@@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
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coresight-etm4x-sysfs.o
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obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
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obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
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obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
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700
drivers/hwtracing/coresight/coresight-cpu-debug.c
Normal file
700
drivers/hwtracing/coresight/coresight-cpu-debug.c
Normal file
@@ -0,0 +1,700 @@
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/*
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* Copyright (c) 2017 Linaro Limited. All rights reserved.
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*
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* Author: Leo Yan <leo.yan@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/amba/bus.h>
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#include <linux/coresight.h>
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#include <linux/cpu.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pm_qos.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include "coresight-priv.h"
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#define EDPCSR 0x0A0
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#define EDCIDSR 0x0A4
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#define EDVIDSR 0x0A8
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#define EDPCSR_HI 0x0AC
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#define EDOSLAR 0x300
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#define EDPRCR 0x310
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#define EDPRSR 0x314
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#define EDDEVID1 0xFC4
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#define EDDEVID 0xFC8
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#define EDPCSR_PROHIBITED 0xFFFFFFFF
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/* bits definition for EDPCSR */
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#define EDPCSR_THUMB BIT(0)
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#define EDPCSR_ARM_INST_MASK GENMASK(31, 2)
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#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1)
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/* bits definition for EDPRCR */
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#define EDPRCR_COREPURQ BIT(3)
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#define EDPRCR_CORENPDRQ BIT(0)
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/* bits definition for EDPRSR */
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#define EDPRSR_DLK BIT(6)
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#define EDPRSR_PU BIT(0)
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/* bits definition for EDVIDSR */
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#define EDVIDSR_NS BIT(31)
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#define EDVIDSR_E2 BIT(30)
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#define EDVIDSR_E3 BIT(29)
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#define EDVIDSR_HV BIT(28)
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#define EDVIDSR_VMID GENMASK(7, 0)
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/*
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* bits definition for EDDEVID1:PSCROffset
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*
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* NOTE: armv8 and armv7 have different definition for the register,
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* so consolidate the bits definition as below:
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*
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* 0b0000 - Sample offset applies based on the instruction state, we
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* rely on EDDEVID to check if EDPCSR is implemented or not
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* 0b0001 - No offset applies.
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* 0b0010 - No offset applies, but do not use in AArch32 mode
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*
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*/
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#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0)
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#define EDDEVID1_PCSR_OFFSET_INS_SET (0x0)
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#define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 (0x2)
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/* bits definition for EDDEVID */
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#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0)
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#define EDDEVID_IMPL_EDPCSR (0x1)
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#define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2)
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#define EDDEVID_IMPL_FULL (0x3)
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#define DEBUG_WAIT_SLEEP 1000
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#define DEBUG_WAIT_TIMEOUT 32000
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struct debug_drvdata {
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void __iomem *base;
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struct device *dev;
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int cpu;
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bool edpcsr_present;
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bool edcidsr_present;
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bool edvidsr_present;
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bool pc_has_offset;
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u32 edpcsr;
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u32 edpcsr_hi;
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u32 edprsr;
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u32 edvidsr;
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u32 edcidsr;
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};
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static DEFINE_MUTEX(debug_lock);
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static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata);
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static int debug_count;
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static struct dentry *debug_debugfs_dir;
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static bool debug_enable;
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module_param_named(enable, debug_enable, bool, 0600);
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MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
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static void debug_os_unlock(struct debug_drvdata *drvdata)
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{
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/* Unlocks the debug registers */
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writel_relaxed(0x0, drvdata->base + EDOSLAR);
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/* Make sure the registers are unlocked before accessing */
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wmb();
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}
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/*
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* According to ARM DDI 0487A.k, before access external debug
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* registers should firstly check the access permission; if any
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* below condition has been met then cannot access debug
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* registers to avoid lockup issue:
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*
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* - CPU power domain is powered off;
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* - The OS Double Lock is locked;
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*
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* By checking EDPRSR can get to know if meet these conditions.
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*/
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static bool debug_access_permitted(struct debug_drvdata *drvdata)
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{
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/* CPU is powered off */
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if (!(drvdata->edprsr & EDPRSR_PU))
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return false;
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/* The OS Double Lock is locked */
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if (drvdata->edprsr & EDPRSR_DLK)
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return false;
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return true;
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}
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static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
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{
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u32 edprcr;
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try_again:
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/*
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* Send request to power management controller and assert
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* DBGPWRUPREQ signal; if power management controller has
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* sane implementation, it should enable CPU power domain
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* in case CPU is in low power state.
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*/
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edprcr = readl_relaxed(drvdata->base + EDPRCR);
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edprcr |= EDPRCR_COREPURQ;
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writel_relaxed(edprcr, drvdata->base + EDPRCR);
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/* Wait for CPU to be powered up (timeout~=32ms) */
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if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR,
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drvdata->edprsr, (drvdata->edprsr & EDPRSR_PU),
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DEBUG_WAIT_SLEEP, DEBUG_WAIT_TIMEOUT)) {
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/*
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* Unfortunately the CPU cannot be powered up, so return
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* back and later has no permission to access other
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* registers. For this case, should disable CPU low power
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* states to ensure CPU power domain is enabled!
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*/
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dev_err(drvdata->dev, "%s: power up request for CPU%d failed\n",
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__func__, drvdata->cpu);
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return;
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}
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/*
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* At this point the CPU is powered up, so set the no powerdown
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* request bit so we don't lose power and emulate power down.
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*/
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edprcr = readl_relaxed(drvdata->base + EDPRCR);
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edprcr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
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writel_relaxed(edprcr, drvdata->base + EDPRCR);
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drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR);
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/* The core power domain got switched off on use, try again */
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if (unlikely(!(drvdata->edprsr & EDPRSR_PU)))
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goto try_again;
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}
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static void debug_read_regs(struct debug_drvdata *drvdata)
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{
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u32 save_edprcr;
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CS_UNLOCK(drvdata->base);
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/* Unlock os lock */
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debug_os_unlock(drvdata);
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/* Save EDPRCR register */
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save_edprcr = readl_relaxed(drvdata->base + EDPRCR);
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/*
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* Ensure CPU power domain is enabled to let registers
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* are accessiable.
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*/
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debug_force_cpu_powered_up(drvdata);
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if (!debug_access_permitted(drvdata))
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goto out;
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drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR);
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/*
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* As described in ARM DDI 0487A.k, if the processing
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* element (PE) is in debug state, or sample-based
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* profiling is prohibited, EDPCSR reads as 0xFFFFFFFF;
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* EDCIDSR, EDVIDSR and EDPCSR_HI registers also become
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* UNKNOWN state. So directly bail out for this case.
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*/
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if (drvdata->edpcsr == EDPCSR_PROHIBITED)
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goto out;
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/*
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* A read of the EDPCSR normally has the side-effect of
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* indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI;
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* at this point it's safe to read value from them.
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*/
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if (IS_ENABLED(CONFIG_64BIT))
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drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI);
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if (drvdata->edcidsr_present)
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drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR);
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|
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if (drvdata->edvidsr_present)
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drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR);
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out:
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/* Restore EDPRCR register */
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writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
|
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CS_LOCK(drvdata->base);
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}
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||||
|
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#ifdef CONFIG_64BIT
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||||
static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
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||||
{
|
||||
return (unsigned long)drvdata->edpcsr_hi << 32 |
|
||||
(unsigned long)drvdata->edpcsr;
|
||||
}
|
||||
#else
|
||||
static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
|
||||
{
|
||||
unsigned long arm_inst_offset = 0, thumb_inst_offset = 0;
|
||||
unsigned long pc;
|
||||
|
||||
pc = (unsigned long)drvdata->edpcsr;
|
||||
|
||||
if (drvdata->pc_has_offset) {
|
||||
arm_inst_offset = 8;
|
||||
thumb_inst_offset = 4;
|
||||
}
|
||||
|
||||
/* Handle thumb instruction */
|
||||
if (pc & EDPCSR_THUMB) {
|
||||
pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset;
|
||||
return pc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle arm instruction offset, if the arm instruction
|
||||
* is not 4 byte alignment then it's possible the case
|
||||
* for implementation defined; keep original value for this
|
||||
* case and print info for notice.
|
||||
*/
|
||||
if (pc & BIT(1))
|
||||
dev_emerg(drvdata->dev,
|
||||
"Instruction offset is implementation defined\n");
|
||||
else
|
||||
pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset;
|
||||
|
||||
return pc;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void debug_dump_regs(struct debug_drvdata *drvdata)
|
||||
{
|
||||
struct device *dev = drvdata->dev;
|
||||
unsigned long pc;
|
||||
|
||||
dev_emerg(dev, " EDPRSR: %08x (Power:%s DLK:%s)\n",
|
||||
drvdata->edprsr,
|
||||
drvdata->edprsr & EDPRSR_PU ? "On" : "Off",
|
||||
drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock");
|
||||
|
||||
if (!debug_access_permitted(drvdata)) {
|
||||
dev_emerg(dev, "No permission to access debug registers!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (drvdata->edpcsr == EDPCSR_PROHIBITED) {
|
||||
dev_emerg(dev, "CPU is in Debug state or profiling is prohibited!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pc = debug_adjust_pc(drvdata);
|
||||
dev_emerg(dev, " EDPCSR: [<%p>] %pS\n", (void *)pc, (void *)pc);
|
||||
|
||||
if (drvdata->edcidsr_present)
|
||||
dev_emerg(dev, " EDCIDSR: %08x\n", drvdata->edcidsr);
|
||||
|
||||
if (drvdata->edvidsr_present)
|
||||
dev_emerg(dev, " EDVIDSR: %08x (State:%s Mode:%s Width:%dbits VMID:%x)\n",
|
||||
drvdata->edvidsr,
|
||||
drvdata->edvidsr & EDVIDSR_NS ?
|
||||
"Non-secure" : "Secure",
|
||||
drvdata->edvidsr & EDVIDSR_E3 ? "EL3" :
|
||||
(drvdata->edvidsr & EDVIDSR_E2 ?
|
||||
"EL2" : "EL1/0"),
|
||||
drvdata->edvidsr & EDVIDSR_HV ? 64 : 32,
|
||||
drvdata->edvidsr & (u32)EDVIDSR_VMID);
|
||||
}
|
||||
|
||||
static void debug_init_arch_data(void *info)
|
||||
{
|
||||
struct debug_drvdata *drvdata = info;
|
||||
u32 mode, pcsr_offset;
|
||||
u32 eddevid, eddevid1;
|
||||
|
||||
CS_UNLOCK(drvdata->base);
|
||||
|
||||
/* Read device info */
|
||||
eddevid = readl_relaxed(drvdata->base + EDDEVID);
|
||||
eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
|
||||
|
||||
CS_LOCK(drvdata->base);
|
||||
|
||||
/* Parse implementation feature */
|
||||
mode = eddevid & EDDEVID_PCSAMPLE_MODE;
|
||||
pcsr_offset = eddevid1 & EDDEVID1_PCSR_OFFSET_MASK;
|
||||
|
||||
drvdata->edpcsr_present = false;
|
||||
drvdata->edcidsr_present = false;
|
||||
drvdata->edvidsr_present = false;
|
||||
drvdata->pc_has_offset = false;
|
||||
|
||||
switch (mode) {
|
||||
case EDDEVID_IMPL_FULL:
|
||||
drvdata->edvidsr_present = true;
|
||||
/* Fall through */
|
||||
case EDDEVID_IMPL_EDPCSR_EDCIDSR:
|
||||
drvdata->edcidsr_present = true;
|
||||
/* Fall through */
|
||||
case EDDEVID_IMPL_EDPCSR:
|
||||
/*
|
||||
* In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to
|
||||
* define if has the offset for PC sampling value; if read
|
||||
* back EDDEVID1.PCSROffset == 0x2, then this means the debug
|
||||
* module does not sample the instruction set state when
|
||||
* armv8 CPU in AArch32 state.
|
||||
*/
|
||||
drvdata->edpcsr_present =
|
||||
((IS_ENABLED(CONFIG_64BIT) && pcsr_offset != 0) ||
|
||||
(pcsr_offset != EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32));
|
||||
|
||||
drvdata->pc_has_offset =
|
||||
(pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Dump out information on panic.
|
||||
*/
|
||||
static int debug_notifier_call(struct notifier_block *self,
|
||||
unsigned long v, void *p)
|
||||
{
|
||||
int cpu;
|
||||
struct debug_drvdata *drvdata;
|
||||
|
||||
mutex_lock(&debug_lock);
|
||||
|
||||
/* Bail out if the functionality is disabled */
|
||||
if (!debug_enable)
|
||||
goto skip_dump;
|
||||
|
||||
pr_emerg("ARM external debug module:\n");
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
drvdata = per_cpu(debug_drvdata, cpu);
|
||||
if (!drvdata)
|
||||
continue;
|
||||
|
||||
dev_emerg(drvdata->dev, "CPU[%d]:\n", drvdata->cpu);
|
||||
|
||||
debug_read_regs(drvdata);
|
||||
debug_dump_regs(drvdata);
|
||||
}
|
||||
|
||||
skip_dump:
|
||||
mutex_unlock(&debug_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct notifier_block debug_notifier = {
|
||||
.notifier_call = debug_notifier_call,
|
||||
};
|
||||
|
||||
static int debug_enable_func(void)
|
||||
{
|
||||
struct debug_drvdata *drvdata;
|
||||
int cpu, ret = 0;
|
||||
cpumask_t mask;
|
||||
|
||||
/*
|
||||
* Use cpumask to track which debug power domains have
|
||||
* been powered on and use it to handle failure case.
|
||||
*/
|
||||
cpumask_clear(&mask);
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
drvdata = per_cpu(debug_drvdata, cpu);
|
||||
if (!drvdata)
|
||||
continue;
|
||||
|
||||
ret = pm_runtime_get_sync(drvdata->dev);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
else
|
||||
cpumask_set_cpu(cpu, &mask);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
/*
|
||||
* If pm_runtime_get_sync() has failed, need rollback on
|
||||
* all the other CPUs that have been enabled before that.
|
||||
*/
|
||||
for_each_cpu(cpu, &mask) {
|
||||
drvdata = per_cpu(debug_drvdata, cpu);
|
||||
pm_runtime_put_noidle(drvdata->dev);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int debug_disable_func(void)
|
||||
{
|
||||
struct debug_drvdata *drvdata;
|
||||
int cpu, ret, err = 0;
|
||||
|
||||
/*
|
||||
* Disable debug power domains, records the error and keep
|
||||
* circling through all other CPUs when an error has been
|
||||
* encountered.
|
||||
*/
|
||||
for_each_possible_cpu(cpu) {
|
||||
drvdata = per_cpu(debug_drvdata, cpu);
|
||||
if (!drvdata)
|
||||
continue;
|
||||
|
||||
ret = pm_runtime_put(drvdata->dev);
|
||||
if (ret < 0)
|
||||
err = ret;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static ssize_t debug_func_knob_write(struct file *f,
|
||||
const char __user *buf, size_t count, loff_t *ppos)
|
||||
{
|
||||
u8 val;
|
||||
int ret;
|
||||
|
||||
ret = kstrtou8_from_user(buf, count, 2, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mutex_lock(&debug_lock);
|
||||
|
||||
if (val == debug_enable)
|
||||
goto out;
|
||||
|
||||
if (val)
|
||||
ret = debug_enable_func();
|
||||
else
|
||||
ret = debug_disable_func();
|
||||
|
||||
if (ret) {
|
||||
pr_err("%s: unable to %s debug function: %d\n",
|
||||
__func__, val ? "enable" : "disable", ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
debug_enable = val;
|
||||
out:
|
||||
ret = count;
|
||||
err:
|
||||
mutex_unlock(&debug_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t debug_func_knob_read(struct file *f,
|
||||
char __user *ubuf, size_t count, loff_t *ppos)
|
||||
{
|
||||
ssize_t ret;
|
||||
char buf[3];
|
||||
|
||||
mutex_lock(&debug_lock);
|
||||
snprintf(buf, sizeof(buf), "%d\n", debug_enable);
|
||||
mutex_unlock(&debug_lock);
|
||||
|
||||
ret = simple_read_from_buffer(ubuf, count, ppos, buf, sizeof(buf));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct file_operations debug_func_knob_fops = {
|
||||
.open = simple_open,
|
||||
.read = debug_func_knob_read,
|
||||
.write = debug_func_knob_write,
|
||||
};
|
||||
|
||||
static int debug_func_init(void)
|
||||
{
|
||||
struct dentry *file;
|
||||
int ret;
|
||||
|
||||
/* Create debugfs node */
|
||||
debug_debugfs_dir = debugfs_create_dir("coresight_cpu_debug", NULL);
|
||||
if (!debug_debugfs_dir) {
|
||||
pr_err("%s: unable to create debugfs directory\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
file = debugfs_create_file("enable", 0644, debug_debugfs_dir, NULL,
|
||||
&debug_func_knob_fops);
|
||||
if (!file) {
|
||||
pr_err("%s: unable to create enable knob file\n", __func__);
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Register function to be called for panic */
|
||||
ret = atomic_notifier_chain_register(&panic_notifier_list,
|
||||
&debug_notifier);
|
||||
if (ret) {
|
||||
pr_err("%s: unable to register notifier: %d\n",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
debugfs_remove_recursive(debug_debugfs_dir);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void debug_func_exit(void)
|
||||
{
|
||||
atomic_notifier_chain_unregister(&panic_notifier_list,
|
||||
&debug_notifier);
|
||||
debugfs_remove_recursive(debug_debugfs_dir);
|
||||
}
|
||||
|
||||
static int debug_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct device *dev = &adev->dev;
|
||||
struct debug_drvdata *drvdata;
|
||||
struct resource *res = &adev->res;
|
||||
struct device_node *np = adev->dev.of_node;
|
||||
int ret;
|
||||
|
||||
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata->cpu = np ? of_coresight_get_cpu(np) : 0;
|
||||
if (per_cpu(debug_drvdata, drvdata->cpu)) {
|
||||
dev_err(dev, "CPU%d drvdata has already been initialized\n",
|
||||
drvdata->cpu);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
drvdata->dev = &adev->dev;
|
||||
amba_set_drvdata(adev, drvdata);
|
||||
|
||||
/* Validity for the resource is already checked by the AMBA core */
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
drvdata->base = base;
|
||||
|
||||
get_online_cpus();
|
||||
per_cpu(debug_drvdata, drvdata->cpu) = drvdata;
|
||||
ret = smp_call_function_single(drvdata->cpu, debug_init_arch_data,
|
||||
drvdata, 1);
|
||||
put_online_cpus();
|
||||
|
||||
if (ret) {
|
||||
dev_err(dev, "CPU%d debug arch init failed\n", drvdata->cpu);
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!drvdata->edpcsr_present) {
|
||||
dev_err(dev, "CPU%d sample-based profiling isn't implemented\n",
|
||||
drvdata->cpu);
|
||||
ret = -ENXIO;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!debug_count++) {
|
||||
ret = debug_func_init();
|
||||
if (ret)
|
||||
goto err_func_init;
|
||||
}
|
||||
|
||||
mutex_lock(&debug_lock);
|
||||
/* Turn off debug power domain if debugging is disabled */
|
||||
if (!debug_enable)
|
||||
pm_runtime_put(dev);
|
||||
mutex_unlock(&debug_lock);
|
||||
|
||||
dev_info(dev, "Coresight debug-CPU%d initialized\n", drvdata->cpu);
|
||||
return 0;
|
||||
|
||||
err_func_init:
|
||||
debug_count--;
|
||||
err:
|
||||
per_cpu(debug_drvdata, drvdata->cpu) = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int debug_remove(struct amba_device *adev)
|
||||
{
|
||||
struct device *dev = &adev->dev;
|
||||
struct debug_drvdata *drvdata = amba_get_drvdata(adev);
|
||||
|
||||
per_cpu(debug_drvdata, drvdata->cpu) = NULL;
|
||||
|
||||
mutex_lock(&debug_lock);
|
||||
/* Turn off debug power domain before rmmod the module */
|
||||
if (debug_enable)
|
||||
pm_runtime_put(dev);
|
||||
mutex_unlock(&debug_lock);
|
||||
|
||||
if (!--debug_count)
|
||||
debug_func_exit();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct amba_id debug_ids[] = {
|
||||
{ /* Debug for Cortex-A53 */
|
||||
.id = 0x000bbd03,
|
||||
.mask = 0x000fffff,
|
||||
},
|
||||
{ /* Debug for Cortex-A57 */
|
||||
.id = 0x000bbd07,
|
||||
.mask = 0x000fffff,
|
||||
},
|
||||
{ /* Debug for Cortex-A72 */
|
||||
.id = 0x000bbd08,
|
||||
.mask = 0x000fffff,
|
||||
},
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct amba_driver debug_driver = {
|
||||
.drv = {
|
||||
.name = "coresight-cpu-debug",
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = debug_probe,
|
||||
.remove = debug_remove,
|
||||
.id_table = debug_ids,
|
||||
};
|
||||
|
||||
module_amba_driver(debug_driver);
|
||||
|
||||
MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
|
||||
MODULE_DESCRIPTION("ARM Coresight CPU Debug Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -375,7 +375,7 @@ static void etb_update_buffer(struct coresight_device *csdev,
|
||||
|
||||
/*
|
||||
* Entries should be aligned to the frame size. If they are not
|
||||
* go back to the last alignement point to give decoding tools a
|
||||
* go back to the last alignment point to give decoding tools a
|
||||
* chance to fix things.
|
||||
*/
|
||||
if (write_ptr % ETB_FRAME_SIZE_WORDS) {
|
||||
@@ -675,11 +675,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
|
||||
drvdata->buf = devm_kzalloc(dev,
|
||||
drvdata->buffer_depth * 4, GFP_KERNEL);
|
||||
if (!drvdata->buf) {
|
||||
dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
|
||||
drvdata->buffer_depth * 4);
|
||||
if (!drvdata->buf)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
desc.type = CORESIGHT_DEV_TYPE_SINK;
|
||||
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
|
||||
|
||||
@@ -201,6 +201,7 @@ static void *etm_setup_aux(int event_cpu, void **pages,
|
||||
event_data = alloc_event_data(event_cpu);
|
||||
if (!event_data)
|
||||
return NULL;
|
||||
INIT_WORK(&event_data->work, free_event_data);
|
||||
|
||||
/*
|
||||
* In theory nothing prevent tracers in a trace session from being
|
||||
@@ -217,8 +218,6 @@ static void *etm_setup_aux(int event_cpu, void **pages,
|
||||
if (!sink)
|
||||
goto err;
|
||||
|
||||
INIT_WORK(&event_data->work, free_event_data);
|
||||
|
||||
mask = &event_data->mask;
|
||||
|
||||
/* Setup the path for each CPU in a trace session */
|
||||
|
||||
@@ -166,9 +166,6 @@ out:
|
||||
if (!used)
|
||||
kfree(buf);
|
||||
|
||||
if (!ret)
|
||||
dev_info(drvdata->dev, "TMC-ETB/ETF enabled\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -204,15 +201,27 @@ out:
|
||||
|
||||
static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode)
|
||||
{
|
||||
int ret;
|
||||
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
|
||||
|
||||
switch (mode) {
|
||||
case CS_MODE_SYSFS:
|
||||
return tmc_enable_etf_sink_sysfs(csdev);
|
||||
ret = tmc_enable_etf_sink_sysfs(csdev);
|
||||
break;
|
||||
case CS_MODE_PERF:
|
||||
return tmc_enable_etf_sink_perf(csdev);
|
||||
ret = tmc_enable_etf_sink_perf(csdev);
|
||||
break;
|
||||
/* We shouldn't be here */
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
/* We shouldn't be here */
|
||||
return -EINVAL;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_info(drvdata->dev, "TMC-ETB/ETF enabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tmc_disable_etf_sink(struct coresight_device *csdev)
|
||||
@@ -273,7 +282,7 @@ static void tmc_disable_etf_link(struct coresight_device *csdev,
|
||||
drvdata->mode = CS_MODE_DISABLED;
|
||||
spin_unlock_irqrestore(&drvdata->spinlock, flags);
|
||||
|
||||
dev_info(drvdata->dev, "TMC disabled\n");
|
||||
dev_info(drvdata->dev, "TMC-ETF disabled\n");
|
||||
}
|
||||
|
||||
static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu,
|
||||
|
||||
@@ -362,6 +362,13 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
desc.type = CORESIGHT_DEV_TYPE_SINK;
|
||||
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
|
||||
desc.ops = &tmc_etr_cs_ops;
|
||||
/*
|
||||
* ETR configuration uses a 40-bit AXI master in place of
|
||||
* the embedded SRAM of ETB/ETF.
|
||||
*/
|
||||
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
|
||||
if (ret)
|
||||
goto out;
|
||||
} else {
|
||||
desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
|
||||
desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
|
||||
|
||||
@@ -253,14 +253,22 @@ static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void coresight_disable_source(struct coresight_device *csdev)
|
||||
/**
|
||||
* coresight_disable_source - Drop the reference count by 1 and disable
|
||||
* the device if there are no users left.
|
||||
*
|
||||
* @csdev - The coresight device to disable
|
||||
*
|
||||
* Returns true if the device has been disabled.
|
||||
*/
|
||||
static bool coresight_disable_source(struct coresight_device *csdev)
|
||||
{
|
||||
if (atomic_dec_return(csdev->refcnt) == 0) {
|
||||
if (source_ops(csdev)->disable) {
|
||||
if (source_ops(csdev)->disable)
|
||||
source_ops(csdev)->disable(csdev, NULL);
|
||||
csdev->enable = false;
|
||||
}
|
||||
csdev->enable = false;
|
||||
}
|
||||
return !csdev->enable;
|
||||
}
|
||||
|
||||
void coresight_disable_path(struct list_head *path)
|
||||
@@ -550,6 +558,9 @@ int coresight_enable(struct coresight_device *csdev)
|
||||
int cpu, ret = 0;
|
||||
struct coresight_device *sink;
|
||||
struct list_head *path;
|
||||
enum coresight_dev_subtype_source subtype;
|
||||
|
||||
subtype = csdev->subtype.source_subtype;
|
||||
|
||||
mutex_lock(&coresight_mutex);
|
||||
|
||||
@@ -557,8 +568,16 @@ int coresight_enable(struct coresight_device *csdev)
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (csdev->enable)
|
||||
if (csdev->enable) {
|
||||
/*
|
||||
* There could be multiple applications driving the software
|
||||
* source. So keep the refcount for each such user when the
|
||||
* source is already enabled.
|
||||
*/
|
||||
if (subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE)
|
||||
atomic_inc(csdev->refcnt);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Search for a valid sink for this session but don't reset the
|
||||
@@ -585,7 +604,7 @@ int coresight_enable(struct coresight_device *csdev)
|
||||
if (ret)
|
||||
goto err_source;
|
||||
|
||||
switch (csdev->subtype.source_subtype) {
|
||||
switch (subtype) {
|
||||
case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
|
||||
/*
|
||||
* When working from sysFS it is important to keep track
|
||||
@@ -629,7 +648,7 @@ void coresight_disable(struct coresight_device *csdev)
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (!csdev->enable)
|
||||
if (!csdev->enable || !coresight_disable_source(csdev))
|
||||
goto out;
|
||||
|
||||
switch (csdev->subtype.source_subtype) {
|
||||
@@ -647,7 +666,6 @@ void coresight_disable(struct coresight_device *csdev)
|
||||
break;
|
||||
}
|
||||
|
||||
coresight_disable_source(csdev);
|
||||
coresight_disable_path(path);
|
||||
coresight_release_path(path);
|
||||
|
||||
|
||||
@@ -52,7 +52,7 @@ of_coresight_get_endpoint_device(struct device_node *endpoint)
|
||||
endpoint, of_dev_node_match);
|
||||
}
|
||||
|
||||
static void of_coresight_get_ports(struct device_node *node,
|
||||
static void of_coresight_get_ports(const struct device_node *node,
|
||||
int *nr_inport, int *nr_outport)
|
||||
{
|
||||
struct device_node *ep = NULL;
|
||||
@@ -101,14 +101,40 @@ static int of_coresight_alloc_memory(struct device *dev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct coresight_platform_data *of_get_coresight_platform_data(
|
||||
struct device *dev, struct device_node *node)
|
||||
int of_coresight_get_cpu(const struct device_node *node)
|
||||
{
|
||||
int i = 0, ret = 0, cpu;
|
||||
int cpu;
|
||||
bool found;
|
||||
struct device_node *dn, *np;
|
||||
|
||||
dn = of_parse_phandle(node, "cpu", 0);
|
||||
|
||||
/* Affinity defaults to CPU0 */
|
||||
if (!dn)
|
||||
return 0;
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
np = of_cpu_device_node_get(cpu);
|
||||
found = (dn == np);
|
||||
of_node_put(np);
|
||||
if (found)
|
||||
break;
|
||||
}
|
||||
of_node_put(dn);
|
||||
|
||||
/* Affinity to CPU0 if no cpu nodes are found */
|
||||
return found ? cpu : 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
|
||||
|
||||
struct coresight_platform_data *
|
||||
of_get_coresight_platform_data(struct device *dev,
|
||||
const struct device_node *node)
|
||||
{
|
||||
int i = 0, ret = 0;
|
||||
struct coresight_platform_data *pdata;
|
||||
struct of_endpoint endpoint, rendpoint;
|
||||
struct device *rdev;
|
||||
struct device_node *dn;
|
||||
struct device_node *ep = NULL;
|
||||
struct device_node *rparent = NULL;
|
||||
struct device_node *rport = NULL;
|
||||
@@ -175,16 +201,7 @@ struct coresight_platform_data *of_get_coresight_platform_data(
|
||||
} while (ep);
|
||||
}
|
||||
|
||||
/* Affinity defaults to CPU0 */
|
||||
pdata->cpu = 0;
|
||||
dn = of_parse_phandle(node, "cpu", 0);
|
||||
for (cpu = 0; dn && cpu < nr_cpu_ids; cpu++) {
|
||||
if (dn == of_get_cpu_node(cpu, NULL)) {
|
||||
pdata->cpu = cpu;
|
||||
break;
|
||||
}
|
||||
}
|
||||
of_node_put(dn);
|
||||
pdata->cpu = of_coresight_get_cpu(node);
|
||||
|
||||
return pdata;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user