drm/radeon: fix endian bugs in radeon_atom_get_clock_dividers() (v3)
v2: fix copy paste typo. v3: clarify new union member Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -458,6 +458,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
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union
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{
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ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
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ULONG ulClockParams; //ULONG access for BE
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ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
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};
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UCHAR ucRefDiv; //Output Parameter
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@@ -490,6 +491,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
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union
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{
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ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
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ULONG ulClockParams; //ULONG access for BE
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ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
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};
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UCHAR ucRefDiv; //Output Parameter
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