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Merge tag 'lpc32xx-dt-for-5.2' of https://github.com/vzapolskiy/linux-lpc32xx into arm/dt

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ARM: lpc32xx: devicetree updates for v5.2

Here are the changes for ARM NXP LPC32xx devicetree files:

* disabled I2S and MAC controllers by default,
* set default #address-cells = <1> / #size-cells = <0> for SPI slaves,
* fix notation of hexadecimal values,
* switched lpc32xx.dtsi to SPDX license identifier.

* tag 'lpc32xx-dt-for-5.2' of https://github.com/vzapolskiy/linux-lpc32xx:
  ARM: dts: lpc32xx: use SPDX license identifier
  ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes
  ARM: dts: lpc32xx: disable MAC controller by default
  ARM: dts: lpc32xx: disable I2S controllers by default
  ARM: dts: lpc32xx: change hexadecimal values to lower case

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2019-04-29 09:24:53 -07:00
parent 0b6cf36a47 d5a71e4646
commit f45f5182d7
3 changed files with 24 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/lpc3250-ea3250.dts
View File

@@ -201,6 +201,7 @@
&mac {
phy-mode = "rmii";
use-iram;
status = "okay";
};
/* Here, choose exactly one from: ohci, usbd */

3
arch/arm/boot/dts/lpc3250-phy3250.dts
View File

@@ -134,6 +134,7 @@
&mac {
phy-mode = "rmii";
use-iram;
status = "okay";
};
/* Here, choose exactly one from: ohci, usbd */
@@ -201,8 +202,6 @@
};
&ssp0 {
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
cs-gpios = <&gpio 3 5 0>;
status = "okay";

38
arch/arm/boot/dts/lpc32xx.dtsi
View File

@@ -1,14 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* NXP LPC32xx SoC
*
* Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/clock/lpc32xx-clock.h>
@@ -152,6 +147,7 @@
reg = <0x31060000 0x1000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_MAC>;
status = "disabled";
};
emc: memory-controller@31080000 {
@@ -185,6 +181,8 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SSP0>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -192,6 +190,8 @@
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -205,6 +205,8 @@
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SSP1>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@@ -212,12 +214,15 @@
compatible = "nxp,lpc3220-spi";
reg = <0x20090000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2s0: i2s@20094000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x20094000 0x1000>;
status = "disabled";
};
sd: sd@20098000 {
@@ -232,7 +237,8 @@
i2s1: i2s@2009c000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x2009C000 0x1000>;
reg = <0x2009c000 0x1000>;
status = "disabled";
};
/* UART5 first since it is the default console, ttyS0 */
@@ -275,7 +281,7 @@
i2c1: i2c@400a0000 {
compatible = "nxp,pnx-i2c";
reg = <0x400A0000 0x100>;
reg = <0x400a0000 0x100>;
interrupt-parent = <&sic1>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
@@ -286,7 +292,7 @@
i2c2: i2c@400a8000 {
compatible = "nxp,pnx-i2c";
reg = <0x400A8000 0x100>;
reg = <0x400a8000 0x100>;
interrupt-parent = <&sic1>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
@@ -297,7 +303,7 @@
mpwm: mpwm@400e8000 {
compatible = "nxp,lpc3220-motor-pwm";
reg = <0x400E8000 0x78>;
reg = <0x400e8000 0x78>;
status = "disabled";
#pwm-cells = <2>;
};
@@ -396,7 +402,7 @@
timer4: timer@4002c000 {
compatible = "nxp,lpc3220-timer";
reg = <0x4002C000 0x1000>;
reg = <0x4002c000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk LPC32XX_CLK_TIMER4>;
clock-names = "timerclk";
@@ -414,7 +420,7 @@
watchdog: watchdog@4003c000 {
compatible = "nxp,pnx4008-wdt";
reg = <0x4003C000 0x1000>;
reg = <0x4003c000 0x1000>;
clocks = <&clk LPC32XX_CLK_WDOG>;
};
@@ -453,7 +459,7 @@
timer1: timer@4004c000 {
compatible = "nxp,lpc3220-timer";
reg = <0x4004C000 0x1000>;
reg = <0x4004c000 0x1000>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk LPC32XX_CLK_TIMER1>;
clock-names = "timerclk";
@@ -479,7 +485,7 @@
pwm1: pwm@4005c000 {
compatible = "nxp,lpc3220-pwm";
reg = <0x4005C000 0x4>;
reg = <0x4005c000 0x4>;
clocks = <&clk LPC32XX_CLK_PWM1>;
assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
@@ -488,7 +494,7 @@
pwm2: pwm@4005c004 {
compatible = "nxp,lpc3220-pwm";
reg = <0x4005C004 0x4>;
reg = <0x4005c004 0x4>;
clocks = <&clk LPC32XX_CLK_PWM2>;
assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;