xiaomi-sm8450/android_kernel_xiaomi_sm8450
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کد مسائل تقاضاهای واکشی Actions Packages پروژه‌ها انتشارها دانشنامه فعالیت

Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework

فهرست منبع 
Conflicts:
	arch/sh/kernel/cpu/sh2/setup-sh7619.c
	arch/sh/kernel/cpu/sh2a/setup-mxg.c
	arch/sh/kernel/cpu/sh2a/setup-sh7201.c
	arch/sh/kernel/cpu/sh2a/setup-sh7203.c
	arch/sh/kernel/cpu/sh2a/setup-sh7206.c
	arch/sh/kernel/cpu/sh3/setup-sh7705.c
	arch/sh/kernel/cpu/sh3/setup-sh770x.c
	arch/sh/kernel/cpu/sh3/setup-sh7710.c
	arch/sh/kernel/cpu/sh3/setup-sh7720.c
	arch/sh/kernel/cpu/sh4/setup-sh4-202.c
	arch/sh/kernel/cpu/sh4/setup-sh7750.c
	arch/sh/kernel/cpu/sh4/setup-sh7760.c
	arch/sh/kernel/cpu/sh4a/setup-sh7343.c
	arch/sh/kernel/cpu/sh4a/setup-sh7366.c
	arch/sh/kernel/cpu/sh4a/setup-sh7722.c
	arch/sh/kernel/cpu/sh4a/setup-sh7723.c
	arch/sh/kernel/cpu/sh4a/setup-sh7724.c
	arch/sh/kernel/cpu/sh4a/setup-sh7763.c
	arch/sh/kernel/cpu/sh4a/setup-sh7770.c
	arch/sh/kernel/cpu/sh4a/setup-sh7780.c
	arch/sh/kernel/cpu/sh4a/setup-sh7785.c
	arch/sh/kernel/cpu/sh4a/setup-sh7786.c
	arch/sh/kernel/cpu/sh4a/setup-shx3.c
	arch/sh/kernel/cpu/sh5/setup-sh5.c
	drivers/serial/sh-sci.c
	drivers/serial/sh-sci.h
	include/linux/serial_sci.h
This commit is contained in:
Paul Mundt
2011-01-13 15:06:28 +09:00
والد f8e53553f4 4162cf6497
کامیت f43dc23d5e
26702فایلهای تغییر یافته به همراه4307403 افزوده شده و 2132644 حذف شده
دانلود پرونده وصله دانلود فایل تغییرات diff Expand all files Collapse all files

8
arch/sh/kernel/cpu/sh3/clock-sh3.c
مشاهده پرونده

@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
static void master_clk_init(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
clk->rate *= pfc_divisors[idx];
@@ -40,7 +40,7 @@ static struct clk_ops sh3_master_clk_ops = {
static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
return clk->parent->rate / pfc_divisors[idx];
@@ -52,7 +52,7 @@ static struct clk_ops sh3_module_clk_ops = {
static unsigned long bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
return clk->parent->rate / stc_multipliers[idx];
@@ -64,7 +64,7 @@ static struct clk_ops sh3_bus_clk_ops = {
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
return clk->parent->rate / ifc_divisors[idx];

8
arch/sh/kernel/cpu/sh3/clock-sh7705.c
مشاهده پرونده

@@ -32,7 +32,7 @@ static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
static void master_clk_init(struct clk *clk)
{
clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003];
clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
}
static struct clk_ops sh7705_master_clk_ops = {
@@ -41,7 +41,7 @@ static struct clk_ops sh7705_master_clk_ops = {
static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = ctrl_inw(FRQCR) & 0x0003;
int idx = __raw_readw(FRQCR) & 0x0003;
return clk->parent->rate / pfc_divisors[idx];
}
@@ -51,7 +51,7 @@ static struct clk_ops sh7705_module_clk_ops = {
static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;
return clk->parent->rate / stc_multipliers[idx];
}
@@ -61,7 +61,7 @@ static struct clk_ops sh7705_bus_clk_ops = {
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;
return clk->parent->rate / ifc_divisors[idx];
}

8
arch/sh/kernel/cpu/sh3/clock-sh7706.c
مشاهده پرونده

@@ -24,7 +24,7 @@ static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
static void master_clk_init(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7706_master_clk_ops = {
static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7706_module_clk_ops = {
static unsigned long bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
return clk->parent->rate / stc_multipliers[idx];
@@ -60,7 +60,7 @@ static struct clk_ops sh7706_bus_clk_ops = {
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
return clk->parent->rate / ifc_divisors[idx];

19
arch/sh/kernel/cpu/sh3/clock-sh7709.c
مشاهده پرونده

@@ -22,16 +22,9 @@ static int stc_multipliers[] = { 1, 2, 4, 8, 3, 6, 1, 1 };
static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
static void set_bus_parent(struct clk *clk)
{
struct clk *bus_clk = clk_get(NULL, "bus_clk");
clk->parent = bus_clk;
clk_put(bus_clk);
}
static void master_clk_init(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
clk->rate *= pfc_divisors[idx];
@@ -43,22 +36,19 @@ static struct clk_ops sh7709_master_clk_ops = {
static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
return clk->parent->rate / pfc_divisors[idx];
}
static struct clk_ops sh7709_module_clk_ops = {
#ifdef CLOCK_MODE_0_1_2_7
.init = set_bus_parent,
#endif
.recalc = module_clk_recalc,
};
static unsigned long bus_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = (frqcr & 0x0080) ?
((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
@@ -71,14 +61,13 @@ static struct clk_ops sh7709_bus_clk_ops = {
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
return clk->parent->rate / ifc_divisors[idx];
}
static struct clk_ops sh7709_cpu_clk_ops = {
.init = set_bus_parent,
.recalc = cpu_clk_recalc,
};

8
arch/sh/kernel/cpu/sh3/clock-sh7710.c
مشاهده پرونده

@@ -26,7 +26,7 @@ static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
static void master_clk_init(struct clk *clk)
{
clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007];
clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
}
static struct clk_ops sh7710_master_clk_ops = {
@@ -35,7 +35,7 @@ static struct clk_ops sh7710_master_clk_ops = {
static unsigned long module_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0007);
int idx = (__raw_readw(FRQCR) & 0x0007);
return clk->parent->rate / md_table[idx];
}
@@ -45,7 +45,7 @@ static struct clk_ops sh7710_module_clk_ops = {
static unsigned long bus_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;
return clk->parent->rate / md_table[idx];
}
@@ -55,7 +55,7 @@ static struct clk_ops sh7710_bus_clk_ops = {
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;
return clk->parent->rate / md_table[idx];
}

6
arch/sh/kernel/cpu/sh3/clock-sh7712.c
مشاهده پرونده

@@ -23,7 +23,7 @@ static int divisors[] = { 1, 2, 3, 4, 6 };
static void master_clk_init(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = (frqcr & 0x0300) >> 8;
clk->rate *= multipliers[idx];
@@ -35,7 +35,7 @@ static struct clk_ops sh7712_master_clk_ops = {
static unsigned long module_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = frqcr & 0x0007;
return clk->parent->rate / divisors[idx];
@@ -47,7 +47,7 @@ static struct clk_ops sh7712_module_clk_ops = {
static unsigned long cpu_clk_recalc(struct clk *clk)
{
int frqcr = ctrl_inw(FRQCR);
int frqcr = __raw_readw(FRQCR);
int idx = (frqcr & 0x0030) >> 4;
return clk->parent->rate / divisors[idx];

134
arch/sh/kernel/cpu/sh3/entry.S
مشاهده پرونده

@@ -53,10 +53,6 @@
* syscall #
*
*/
#if defined(CONFIG_KGDB)
NMI_VEC = 0x1c0 ! Must catch early for debounce
#endif
/* Offsets to the stack */
OFF_R0 = 0 /* Return value. New ABI also arg4 */
OFF_R1 = 4 /* New ABI: arg5 */
@@ -71,7 +67,6 @@ OFF_PC = (16*4)
OFF_SR = (16*4+8)
OFF_TRA = (16*4+6*4)
#define k0 r0
#define k1 r1
#define k2 r2
@@ -113,34 +108,33 @@ OFF_TRA = (16*4+6*4)
#if defined(CONFIG_MMU)
.align 2
ENTRY(tlb_miss_load)
bra call_dpf
bra call_handle_tlbmiss
mov #0, r5
.align 2
ENTRY(tlb_miss_store)
bra call_dpf
bra call_handle_tlbmiss
mov #1, r5
.align 2
ENTRY(initial_page_write)
bra call_dpf
mov #1, r5
bra call_handle_tlbmiss
mov #2, r5
.align 2
ENTRY(tlb_protection_violation_load)
bra call_dpf
bra call_do_page_fault
mov #0, r5
.align 2
ENTRY(tlb_protection_violation_store)
bra call_dpf
bra call_do_page_fault
mov #1, r5
call_dpf:
call_handle_tlbmiss:
mov.l 1f, r0
mov r5, r8
mov.l @r0, r6
mov r6, r9
mov.l 2f, r0
sts pr, r10
jsr @r0
@@ -151,16 +145,23 @@ call_dpf:
lds r10, pr
rts
nop
0: mov.l 3f, r0
mov r9, r6
0:
mov r8, r5
call_do_page_fault:
mov.l 1f, r0
mov.l @r0, r6
mov.l 3f, r0
mov.l 4f, r1
mov r15, r4
jmp @r0
mov r15, r4
lds r1, pr
.align 2
1: .long MMU_TEA
2: .long __do_page_fault
2: .long handle_tlbmiss
3: .long do_page_fault
4: .long ret_from_exception
.align 2
ENTRY(address_error_load)
@@ -256,7 +257,7 @@ restore_all:
!
! Calculate new SR value
mov k3, k2 ! original SR value
mov #0xf0, k1
mov #0xfffffff0, k1
extu.b k1, k1
not k1, k1
and k1, k2 ! Mask original SR value
@@ -272,21 +273,12 @@ restore_all:
6: or k0, k2 ! Set the IMASK-bits
ldc k2, ssr
!
#if defined(CONFIG_KGDB)
! Clear in_nmi
mov.l 6f, k0
mov #0, k1
mov.b k1, @k0
#endif
mov k4, r15
rte
nop
.align 2
5: .long 0x00001000 ! DSP
#ifdef CONFIG_KGDB
6: .long in_nmi
#endif
7: .long 0x30000000
! common exception handler
@@ -304,41 +296,8 @@ ENTRY(vbr_base)
!
.balign 256,0,256
general_exception:
#ifndef CONFIG_CPU_SUBTYPE_SHX3
bra handle_exception
sts pr, k3 ! save original pr value in k3
#else
mov.l 1f, k4
mov.l @k4, k4
! Is EXPEVT larger than 0x800?
mov #0x8, k0
shll8 k0
cmp/hs k0, k4
bf 0f
! then add 0x580 (k2 is 0xd80 or 0xda0)
mov #0x58, k0
shll2 k0
shll2 k0
add k0, k4
0:
! Setup stack and save DSP context (k0 contains original r15 on return)
bsr prepare_stack
nop
! Save registers / Switch to bank 0
mov k4, k2 ! keep vector in k2
mov.l 1f, k4 ! SR bits to clear in k4
bsr save_regs ! needs original pr value in k3
nop
bra handle_exception_special
nop
.align 2
1: .long EXPEVT
#endif
! prepare_stack()
! - roll back gRB
@@ -405,6 +364,8 @@ handle_exception:
mov.l @k2, k2 ! read out vector and keep in k2
handle_exception_special:
setup_frame_reg
! Setup return address and jump to exception handler
mov.l 7f, r9 ! fetch return address
stc r2_bank, r0 ! k2 (vector)
@@ -478,23 +439,6 @@ ENTRY(save_low_regs)
!
.balign 512,0,512
ENTRY(handle_interrupt)
#if defined(CONFIG_KGDB)
mov.l 2f, k2
! Debounce (filter nested NMI)
mov.l @k2, k0
mov.l 9f, k1
cmp/eq k1, k0
bf 11f
mov.l 10f, k1
tas.b @k1
bt 11f
rte
nop
.align 2
9: .long NMI_VEC
10: .long in_nmi
11:
#endif /* defined(CONFIG_KGDB) */
sts pr, k3 ! save original pr value in k3
mova exception_data, k0
@@ -507,13 +451,49 @@ ENTRY(handle_interrupt)
bsr save_regs ! needs original pr value in k3
mov #-1, k2 ! default vector kept in k2
setup_frame_reg
stc sr, r0 ! get status register
shlr2 r0
and #0x3c, r0
cmp/eq #0x3c, r0
bf 9f
TRACE_IRQS_OFF
9:
! Setup return address and jump to do_IRQ
mov.l 4f, r9 ! fetch return address
lds r9, pr ! put return address in pr
mov.l 2f, r4
mov.l 3f, r9
mov.l @r4, r4 ! pass INTEVT vector as arg0
shlr2 r4
shlr r4
mov r4, r0 ! save vector->jmp table offset for later
shlr2 r4 ! vector to IRQ# conversion
add #-0x10, r4
cmp/pz r4 ! is it a valid IRQ?
bt 10f
/*
* We got here as a result of taking the INTEVT path for something
* that isn't a valid hard IRQ, therefore we bypass the do_IRQ()
* path and special case the event dispatch instead. This is the
* expected path for the NMI (and any other brilliantly implemented
* exception), which effectively wants regular exception dispatch
* but is unfortunately reported through INTEVT rather than
* EXPEVT. Grr.
*/
mov.l 6f, r9
mov.l @(r0, r9), r9
jmp @r9
mov r15, r8 ! trap handlers take saved regs in r8
10:
jmp @r9 ! Off to do_IRQ() we go.
mov r15, r5 ! pass saved registers as arg1
ENTRY(exception_none)

6
arch/sh/kernel/cpu/sh3/ex.S
مشاهده پرونده

@@ -48,10 +48,8 @@ ENTRY(exception_handling_table)
.long system_call ! Unconditional Trap /* 160 */
.long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
.long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
ENTRY(nmi_slot)
.long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger
ENTRY(user_break_point_trap)
.long break_point_trap /* 1E0 */
.long nmi_trap_handler /* 1C0 */ ! Allow trap to debugger
.long breakpoint_trap_handler /* 1E0 */
/*
* Pad the remainder of the table out, exceptions residing in far

30
arch/sh/kernel/cpu/sh3/probe.c
مشاهده پرونده

@@ -16,7 +16,7 @@
#include <asm/cache.h>
#include <asm/io.h>
int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
void __cpuinit cpu_probe(void)
{
unsigned long addr0, addr1, data0, data1, data2, data3;
@@ -30,23 +30,23 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
/* First, write back & invalidate */
data0 = ctrl_inl(addr0);
ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
data1 = ctrl_inl(addr1);
ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
data0 = __raw_readl(addr0);
__raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
data1 = __raw_readl(addr1);
__raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
/* Next, check if there's shadow or not */
data0 = ctrl_inl(addr0);
data0 = __raw_readl(addr0);
data0 ^= SH_CACHE_VALID;
ctrl_outl(data0, addr0);
data1 = ctrl_inl(addr1);
__raw_writel(data0, addr0);
data1 = __raw_readl(addr1);
data2 = data1 ^ SH_CACHE_VALID;
ctrl_outl(data2, addr1);
data3 = ctrl_inl(addr0);
__raw_writel(data2, addr1);
data3 = __raw_readl(addr0);
/* Lastly, invaliate them. */
ctrl_outl(data0&~SH_CACHE_VALID, addr0);
ctrl_outl(data2&~SH_CACHE_VALID, addr1);
__raw_writel(data0&~SH_CACHE_VALID, addr0);
__raw_writel(data2&~SH_CACHE_VALID, addr1);
back_to_cached();
@@ -94,9 +94,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
boot_cpu_data.dcache.way_incr = (1 << 13);
boot_cpu_data.dcache.entry_mask = 0x1ff0;
boot_cpu_data.dcache.sets = 512;
ctrl_outl(CCR_CACHE_32KB, CCR3_REG);
__raw_writel(CCR_CACHE_32KB, CCR3_REG);
#else
ctrl_outl(CCR_CACHE_16KB, CCR3_REG);
__raw_writel(CCR_CACHE_16KB, CCR3_REG);
#endif
#endif
}
@@ -107,5 +107,5 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
boot_cpu_data.icache = boot_cpu_data.dcache;
return 0;
boot_cpu_data.family = CPU_FAMILY_SH3;
}

2
arch/sh/kernel/cpu/sh3/setup-sh3.c
مشاهده پرونده

@@ -58,7 +58,7 @@ static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
void __init plat_irq_setup_pins(int mode)
{
if (mode == IRQ_MODE_IRQ) {
ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
__raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
register_intc_controller(&intc_desc_irq0123);
return;
}

66
arch/sh/kernel/cpu/sh3/setup-sh7705.c
مشاهده پرونده

@@ -67,32 +67,38 @@ static struct intc_prio_reg prio_registers[] __initdata = {
static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
NULL, prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 56, 56, 56 },
}, {
.mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 52, 52, 52 },
}, {
.flags = 0,
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 56, 56, 56 },
};
static struct platform_device sci_device = {
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = -1,
.id = 0,
.dev = {
.platform_data = sci_platform_data,
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 52, 52, 52 },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
@@ -123,16 +129,13 @@ static struct platform_device rtc_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xfffffe94,
.end = 0xfffffe9f,
.flags = IORESOURCE_MEM,
@@ -154,16 +157,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xfffffea0,
.end = 0xfffffeab,
.flags = IORESOURCE_MEM,
@@ -185,15 +185,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xfffffeac,
.end = 0xfffffebb,
.flags = IORESOURCE_MEM,
@@ -215,10 +212,11 @@ static struct platform_device tmu2_device = {
};
static struct platform_device *sh7705_devices[] __initdata = {
&scif0_device,
&scif1_device,
&tmu0_device,
&tmu1_device,
&tmu2_device,
&sci_device,
&rtc_device,
};
@@ -227,9 +225,11 @@ static int __init sh7705_devices_setup(void)
return platform_add_devices(sh7705_devices,
ARRAY_SIZE(sh7705_devices));
}
__initcall(sh7705_devices_setup);
arch_initcall(sh7705_devices_setup);
static struct platform_device *sh7705_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&tmu0_device,
&tmu1_device,
&tmu2_device,

103
arch/sh/kernel/cpu/sh3/setup-sh770x.c
مشاهده پرونده

@@ -106,62 +106,70 @@ static struct platform_device rtc_device = {
.resource = rtc_resources,
};
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xfffffe80,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCI,
.irqs = { 23, 23, 23, 0 },
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xfffffe80,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCI,
.irqs = { 23, 23, 23, 0 },
};
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = 0,
.dev = {
.platform_data = &scif0_platform_data,
},
};
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
{
.mapbase = 0xa4000150,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 },
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xa4000150,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
{
.mapbase = 0xa4000140,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_IRDA,
.irqs = { 52, 52, 52, 52 },
},
#endif
{
.flags = 0,
}
static struct plat_sci_port scif2_platform_data = {
.mapbase = 0xa4000140,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_IRDA,
.irqs = { 52, 52, 52, 52 },
};
static struct platform_device sci_device = {
static struct platform_device scif2_device = {
.name = "sh-sci",
.id = -1,
.id = 2,
.dev = {
.platform_data = sci_platform_data,
.platform_data = &scif2_platform_data,
},
};
#endif
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xfffffe94,
.end = 0xfffffe9f,
.flags = IORESOURCE_MEM,
@@ -183,16 +191,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xfffffea0,
.end = 0xfffffeab,
.flags = IORESOURCE_MEM,
@@ -214,15 +219,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xfffffeac,
.end = 0xfffffebb,
.flags = IORESOURCE_MEM,
@@ -244,10 +246,19 @@ static struct platform_device tmu2_device = {
};
static struct platform_device *sh770x_devices[] __initdata = {
&scif0_device,
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
&scif1_device,
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
&scif2_device,
#endif
&tmu0_device,
&tmu1_device,
&tmu2_device,
&sci_device,
&rtc_device,
};
@@ -256,9 +267,19 @@ static int __init sh770x_devices_setup(void)
return platform_add_devices(sh770x_devices,
ARRAY_SIZE(sh770x_devices));
}
__initcall(sh770x_devices_setup);
arch_initcall(sh770x_devices_setup);
static struct platform_device *sh770x_early_devices[] __initdata = {
&scif0_device,
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
&scif1_device,
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
&scif2_device,
#endif
&tmu0_device,
&tmu1_device,
&tmu2_device,

69
arch/sh/kernel/cpu/sh3/setup-sh7710.c
مشاهده پرونده

@@ -96,48 +96,50 @@ static struct platform_device rtc_device = {
},
};
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 52, 52, 52, 52 },
}, {
.mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 },
}, {
.flags = 0,
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xa4400000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 52, 52, 52, 52 },
};
static struct platform_device sci_device = {
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = -1,
.id = 0,
.dev = {
.platform_data = sci_platform_data,
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
SCSCR_CKE1 | SCSCR_CKE0,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = { 56, 56, 56, 56 },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xa412fe94,
.end = 0xa412fe9f,
.flags = IORESOURCE_MEM,
@@ -159,16 +161,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xa412fea0,
.end = 0xa412feab,
.flags = IORESOURCE_MEM,
@@ -190,15 +189,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xa412feac,
.end = 0xa412feb5,
.flags = IORESOURCE_MEM,
@@ -220,10 +216,11 @@ static struct platform_device tmu2_device = {
};
static struct platform_device *sh7710_devices[] __initdata = {
&scif0_device,
&scif1_device,
&tmu0_device,
&tmu1_device,
&tmu2_device,
&sci_device,
&rtc_device,
};
@@ -232,9 +229,11 @@ static int __init sh7710_devices_setup(void)
return platform_add_devices(sh7710_devices,
ARRAY_SIZE(sh7710_devices));
}
__initcall(sh7710_devices_setup);
arch_initcall(sh7710_devices_setup);
static struct platform_device *sh7710_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&tmu0_device,
&tmu1_device,
&tmu2_device,

79
arch/sh/kernel/cpu/sh3/setup-sh7720.c
مشاهده پرونده

@@ -48,31 +48,37 @@ static struct platform_device rtc_device = {
},
};
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xa4430000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
}, {
.mapbase = 0xa4438000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
}, {
.flags = 0,
}
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xa4430000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
};
static struct platform_device sci_device = {
static struct platform_device scif0_device = {
.name = "sh-sci",
.id = -1,
.id = 0,
.dev = {
.platform_data = sci_platform_data,
.platform_data = &scif0_platform_data,
},
};
static struct plat_sci_port scif1_platform_data = {
.mapbase = 0xa4438000,
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
};
static struct platform_device scif1_device = {
.name = "sh-sci",
.id = 1,
.dev = {
.platform_data = &scif1_platform_data,
},
};
@@ -128,17 +134,14 @@ static struct platform_device usbf_device = {
};
static struct sh_timer_config cmt0_platform_data = {
.name = "CMT0",
.channel_offset = 0x10,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
static struct resource cmt0_resources[] = {
[0] = {
.name = "CMT0",
.start = 0x044a0010,
.end = 0x044a001b,
.flags = IORESOURCE_MEM,
@@ -160,15 +163,12 @@ static struct platform_device cmt0_device = {
};
static struct sh_timer_config cmt1_platform_data = {
.name = "CMT1",
.channel_offset = 0x20,
.timer_bit = 1,
.clk = "peripheral_clk",
};
static struct resource cmt1_resources[] = {
[0] = {
.name = "CMT1",
.start = 0x044a0020,
.end = 0x044a002b,
.flags = IORESOURCE_MEM,
@@ -190,15 +190,12 @@ static struct platform_device cmt1_device = {
};
static struct sh_timer_config cmt2_platform_data = {
.name = "CMT2",
.channel_offset = 0x30,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource cmt2_resources[] = {
[0] = {
.name = "CMT2",
.start = 0x044a0030,
.end = 0x044a003b,
.flags = IORESOURCE_MEM,
@@ -220,15 +217,12 @@ static struct platform_device cmt2_device = {
};
static struct sh_timer_config cmt3_platform_data = {
.name = "CMT3",
.channel_offset = 0x40,
.timer_bit = 3,
.clk = "peripheral_clk",
};
static struct resource cmt3_resources[] = {
[0] = {
.name = "CMT3",
.start = 0x044a0040,
.end = 0x044a004b,
.flags = IORESOURCE_MEM,
@@ -250,15 +244,12 @@ static struct platform_device cmt3_device = {
};
static struct sh_timer_config cmt4_platform_data = {
.name = "CMT4",
.channel_offset = 0x50,
.timer_bit = 4,
.clk = "peripheral_clk",
};
static struct resource cmt4_resources[] = {
[0] = {
.name = "CMT4",
.start = 0x044a0050,
.end = 0x044a005b,
.flags = IORESOURCE_MEM,
@@ -280,16 +271,13 @@ static struct platform_device cmt4_device = {
};
static struct sh_timer_config tmu0_platform_data = {
.name = "TMU0",
.channel_offset = 0x02,
.timer_bit = 0,
.clk = "peripheral_clk",
.clockevent_rating = 200,
};
static struct resource tmu0_resources[] = {
[0] = {
.name = "TMU0",
.start = 0xa412fe94,
.end = 0xa412fe9f,
.flags = IORESOURCE_MEM,
@@ -311,16 +299,13 @@ static struct platform_device tmu0_device = {
};
static struct sh_timer_config tmu1_platform_data = {
.name = "TMU1",
.channel_offset = 0xe,
.timer_bit = 1,
.clk = "peripheral_clk",
.clocksource_rating = 200,
};
static struct resource tmu1_resources[] = {
[0] = {
.name = "TMU1",
.start = 0xa412fea0,
.end = 0xa412feab,
.flags = IORESOURCE_MEM,
@@ -342,15 +327,12 @@ static struct platform_device tmu1_device = {
};
static struct sh_timer_config tmu2_platform_data = {
.name = "TMU2",
.channel_offset = 0x1a,
.timer_bit = 2,
.clk = "peripheral_clk",
};
static struct resource tmu2_resources[] = {
[0] = {
.name = "TMU2",
.start = 0xa412feac,
.end = 0xa412feb5,
.flags = IORESOURCE_MEM,
@@ -372,6 +354,8 @@ static struct platform_device tmu2_device = {
};
static struct platform_device *sh7720_devices[] __initdata = {
&scif0_device,
&scif1_device,
&cmt0_device,
&cmt1_device,
&cmt2_device,
@@ -381,7 +365,6 @@ static struct platform_device *sh7720_devices[] __initdata = {
&tmu1_device,
&tmu2_device,
&rtc_device,
&sci_device,
&usb_ohci_device,
&usbf_device,
};
@@ -391,9 +374,11 @@ static int __init sh7720_devices_setup(void)
return platform_add_devices(sh7720_devices,
ARRAY_SIZE(sh7720_devices));
}
__initcall(sh7720_devices_setup);
arch_initcall(sh7720_devices_setup);
static struct platform_device *sh7720_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&cmt0_device,
&cmt1_device,
&cmt2_device,