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ARM: LPC32xx: clock.c: jiffies wrapping

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This patch fixes the jiffies wrapping bug in clock.c.

It corrects the timeout computation based on jiffies, uses time_before() for
correct wrapping handling and replaces a binary "&" which should really be a
logical "&&" in a truth expression.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Tested-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Kevin Wells <kevin.wells@nxp.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Roland Stigge
2012-02-08 21:41:02 +01:00
committed by Olof Johansson
parent 8998316c42
commit f40a681885
1 changed files with 6 additions and 6 deletions
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12
arch/arm/mach-lpc32xx/clock.c
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@@ -129,7 +129,7 @@ static struct clk osc_32KHz = {
static int local_pll397_enable(struct clk *clk, int enable) static int local_pll397_enable(struct clk *clk, int enable)
{ {
u32 reg; u32 reg;
unsigned long timeout = 1 + msecs_to_jiffies(10); unsigned long timeout = jiffies + msecs_to_jiffies(10);
reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL); reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
@@ -144,7 +144,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
/* Wait for PLL397 lock */ /* Wait for PLL397 lock */
while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) && LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
(timeout > jiffies)) time_before(jiffies, timeout))
cpu_relax(); cpu_relax();
if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) & if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
@@ -158,7 +158,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
static int local_oscmain_enable(struct clk *clk, int enable) static int local_oscmain_enable(struct clk *clk, int enable)
{ {
u32 reg; u32 reg;
unsigned long timeout = 1 + msecs_to_jiffies(10); unsigned long timeout = jiffies + msecs_to_jiffies(10);
reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL); reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
@@ -173,7 +173,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
/* Wait for main oscillator to start */ /* Wait for main oscillator to start */
while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
LPC32XX_CLKPWR_MOSC_DISABLE) != 0) && LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
(timeout > jiffies)) time_before(jiffies, timeout))
cpu_relax(); cpu_relax();
if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) & if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
@@ -385,7 +385,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
{ {
u32 reg; u32 reg;
int ret = -ENODEV; int ret = -ENODEV;
unsigned long timeout = 1 + msecs_to_jiffies(10); unsigned long timeout = jiffies + msecs_to_jiffies(10);
reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
@@ -398,7 +398,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
/* Wait for PLL lock */ /* Wait for PLL lock */
while ((timeout > jiffies) & (ret == -ENODEV)) { while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS) if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
ret = 0; ret = 0;