Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
- struct thread_info moved off-stack (also touching
include/linux/thread_info.h and include/linux/restart_block.h)
- cpus_have_cap() reworked to avoid __builtin_constant_p() for static
key use (also touching drivers/irqchip/irq-gic-v3.c)
- uprobes support (currently only for native 64-bit tasks)
- Emulation of kernel Privileged Access Never (PAN) using TTBR0_EL1
switching to a reserved page table
- CPU capacity information passing via DT or sysfs (used by the
scheduler)
- support for systems without FP/SIMD (IOW, kernel avoids touching
these registers; there is no soft-float ABI, nor kernel emulation for
AArch64 FP/SIMD)
- handling of hardware watchpoint with unaligned addresses, varied
lengths and offsets from base
- use of the page table contiguous hint for kernel mappings
- hugetlb fixes for sizes involving the contiguous hint
- remove unnecessary I-cache invalidation in flush_cache_range()
- CNTHCTL_EL2 access fix for CPUs with VHE support (ARMv8.1)
- boot-time checks for writable+executable kernel mappings
- simplify asm/opcodes.h and avoid including the 32-bit ARM counterpart
and make the arm64 kernel headers self-consistent (Xen headers patch
merged separately)
- Workaround for broken .inst support in certain binutils versions
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (60 commits)
arm64: Disable PAN on uaccess_enable()
arm64: Work around broken .inst when defective gas is detected
arm64: Add detection code for broken .inst support in binutils
arm64: Remove reference to asm/opcodes.h
arm64: Get rid of asm/opcodes.h
arm64: smp: Prevent raw_smp_processor_id() recursion
arm64: head.S: Fix CNTHCTL_EL2 access on VHE system
arm64: Remove I-cache invalidation from flush_cache_range()
arm64: Enable HIBERNATION in defconfig
arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN
arm64: xen: Enable user access before a privcmd hvc call
arm64: Handle faults caused by inadvertent user access with PAN enabled
arm64: Disable TTBR0_EL1 during normal kernel execution
arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1
arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro
arm64: Factor out PAN enabling/disabling into separate uaccess_* macros
arm64: Update the synchronous external abort fault description
selftests: arm64: add test for unaligned/inexact watchpoint handling
arm64: Allow hw watchpoint of length 3,5,6 and 7
arm64: hw_breakpoint: Handle inexact watchpoint addresses
...
This commit is contained in:
Linus Torvalds
236
Documentation/devicetree/bindings/arm/cpu-capacity.txt
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236
Documentation/devicetree/bindings/arm/cpu-capacity.txt
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==========================================
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ARM CPUs capacity bindings
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==========================================
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==========================================
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1 - Introduction
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==========================================
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ARM systems may be configured to have cpus with different power/performance
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characteristics within the same chip. In this case, additional information has
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to be made available to the kernel for it to be aware of such differences and
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take decisions accordingly.
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==========================================
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2 - CPU capacity definition
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==========================================
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CPU capacity is a number that provides the scheduler information about CPUs
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heterogeneity. Such heterogeneity can come from micro-architectural differences
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(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
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(e.g., SMP systems with multiple frequency domains). Heterogeneity in this
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context is about differing performance characteristics; this binding tries to
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capture a first-order approximation of the relative performance of CPUs.
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CPU capacities are obtained by running a suitable benchmark. This binding makes
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no guarantees on the validity or suitability of any particular benchmark, the
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final capacity should, however, be:
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* A "single-threaded" or CPU affine benchmark
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* Divided by the running frequency of the CPU executing the benchmark
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* Not subject to dynamic frequency scaling of the CPU
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For the time being we however advise usage of the Dhrystone benchmark. What
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above thus becomes:
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CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
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max frequency (with caches enabled). The obtained DMIPS score is then divided
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by the frequency (in MHz) at which the benchmark has been run, so that
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DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
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score obtained in the system.
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==========================================
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3 - capacity-dmips-mhz
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==========================================
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capacity-dmips-mhz is an optional cpu node [1] property: u32 value
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representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
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maximum frequency available to the cpu is then used to calculate the capacity
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value internally used by the kernel.
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capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
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node, it has to be specified for every other cpu nodes, or the system will
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fall back to the default capacity value for every CPU. If cpufreq is not
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available, final capacities are calculated by directly using capacity-dmips-
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mhz values (normalized w.r.t. the highest value found while parsing the DT).
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===========================================
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4 - Examples
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===========================================
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Example 1 (ARM 64-bit, 6-cpu system, two clusters):
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capacities-dmips-mhz are scaled w.r.t. 1024 (cpu@0 and cpu@1)
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supposing cluster0@max-freq=1100 and custer1@max-freq=850,
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final capacities are 1024 for cluster0 and 446 for cluster1
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&A57_0>;
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};
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core1 {
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cpu = <&A57_1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&A53_0>;
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};
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core1 {
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cpu = <&A53_1>;
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};
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core2 {
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cpu = <&A53_2>;
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};
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core3 {
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cpu = <&A53_3>;
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <100>;
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exit-latency-us = <250>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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local-timer-stop;
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entry-latency-us = <800>;
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exit-latency-us = <700>;
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min-residency-us = <2500>;
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};
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};
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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clocks = <&scpi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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};
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_1: cpu@101 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x101>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_2: cpu@102 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x102>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A53_3: cpu@103 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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clocks = <&scpi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <578>;
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};
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A57_L2: l2-cache0 {
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compatible = "cache";
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};
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A53_L2: l2-cache1 {
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compatible = "cache";
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};
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};
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Example 2 (ARM 32-bit, 4-cpu system, two clusters,
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cpus 0,1@1GHz, cpus 2,3@500MHz):
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capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
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cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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capacity-dmips-mhz = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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capacity-dmips-mhz = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x100>;
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capacity-dmips-mhz = <1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x101>;
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capacity-dmips-mhz = <1>;
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};
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};
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===========================================
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5 - References
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===========================================
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[1] ARM Linux Kernel documentation - CPUs bindings
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Documentation/devicetree/bindings/arm/cpus.txt
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@@ -241,6 +241,14 @@ nodes to be present and contain the properties described below.
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# List of phandles to idle state nodes supported
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by this cpu [3].
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- capacity-dmips-mhz
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Usage: Optional
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Value type: <u32>
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Definition:
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# u32 value representing CPU capacity [3] in
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DMIPS/MHz, relative to highest capacity-dmips-mhz
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in the system.
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- rockchip,pmu
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Usage: optional for systems that have an "enable-method"
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property value of "rockchip,rk3066-smp"
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@@ -464,3 +472,5 @@ cpus {
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[2] arm/msm/qcom,kpss-acc.txt
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[3] ARM Linux kernel documentation - idle states bindings
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Documentation/devicetree/bindings/arm/idle-states.txt
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[3] ARM Linux kernel documentation - cpu capacity bindings
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Documentation/devicetree/bindings/arm/cpu-capacity.txt
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