xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: at91: add PWM device node

Browse Source 
Add PWM device node for AT91 series SoC.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Bo Shen
2013-12-19 11:59:17 +08:00
committed by Nicolas Ferre
parent ca594844e4
commit f3ab052786
5 changed files with 46 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/at91sam9263.dtsi
View File

@@ -30,6 +30,7 @@
i2c0 = &i2c0; i2c0 = &i2c0;
ssc0 = &ssc0; ssc0 = &ssc0;
ssc1 = &ssc1; ssc1 = &ssc1;
pwm0 = &pwm0;
}; };
cpus { cpus {
#address-cells = <0>; #address-cells = <0>;
@@ -575,6 +576,14 @@
pinctrl-0 = <&pinctrl_spi1>; pinctrl-0 = <&pinctrl_spi1>;
status = "disabled"; status = "disabled";
}; };
pwm0: pwm@fffb8000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xfffb8000 0x300>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
status = "disabled";
};
}; };
fb0: fb@0x00700000 { fb0: fb@0x00700000 {

9
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@@ -37,6 +37,7 @@
i2c1 = &i2c1; i2c1 = &i2c1;
ssc0 = &ssc0; ssc0 = &ssc0;
ssc1 = &ssc1; ssc1 = &ssc1;
pwm0 = &pwm0;
}; };
cpus { cpus {
#address-cells = <0>; #address-cells = <0>;
@@ -670,6 +671,14 @@
}; };
}; };
pwm0: pwm@fffb8000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xfffb8000 0x300>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
status = "disabled";
};
mmc0: mmc@fff80000 { mmc0: mmc@fff80000 {
compatible = "atmel,hsmci"; compatible = "atmel,hsmci";
reg = <0xfff80000 0x600>; reg = <0xfff80000 0x600>;

9
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@@ -33,6 +33,7 @@
i2c0 = &i2c0; i2c0 = &i2c0;
i2c1 = &i2c1; i2c1 = &i2c1;
ssc0 = &ssc0; ssc0 = &ssc0;
pwm0 = &pwm0;
}; };
cpus { cpus {
#address-cells = <0>; #address-cells = <0>;
@@ -542,6 +543,14 @@
reg = <0xfffffe40 0x10>; reg = <0xfffffe40 0x10>;
status = "disabled"; status = "disabled";
}; };
pwm0: pwm@f8034000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
status = "disabled";
};
}; };
nand0: nand@40000000 { nand0: nand@40000000 {

9
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@@ -35,6 +35,7 @@
i2c1 = &i2c1; i2c1 = &i2c1;
i2c2 = &i2c2; i2c2 = &i2c2;
ssc0 = &ssc0; ssc0 = &ssc0;
pwm0 = &pwm0;
}; };
cpus { cpus {
#address-cells = <0>; #address-cells = <0>;
@@ -762,6 +763,14 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled"; status = "disabled";
}; };
pwm0: pwm@f8034000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
status = "disabled";
};
}; };
nand0: nand@40000000 { nand0: nand@40000000 {

10
arch/arm/boot/dts/sama5d3.dtsi
View File

@@ -37,6 +37,7 @@
i2c2 = &i2c2; i2c2 = &i2c2;
ssc0 = &ssc0; ssc0 = &ssc0;
ssc1 = &ssc1; ssc1 = &ssc1;
pwm0 = &pwm0;
}; };
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
@@ -179,6 +180,15 @@
status = "disabled"; status = "disabled";
}; };
pwm0: pwm@f002c000 {
compatible = "atmel,sama5d3-pwm";
reg = <0xf002c000 0x300>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
clocks = <&pwm_clk>;
status = "disabled";
};
isi: isi@f0034000 { isi: isi@f0034000 {
compatible = "atmel,at91sam9g45-isi"; compatible = "atmel,at91sam9g45-isi";
reg = <0xf0034000 0x4000>; reg = <0xf0034000 0x4000>;