Merge branch 'linus' into perf/core
Reason: Further changes conflict with upstream fixes Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
@@ -118,7 +118,7 @@ static unsigned int gsi_to_irq(unsigned int gsi)
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if (gsi >= NR_IRQS_LEGACY)
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irq = gsi;
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else
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irq = gsi_end + 1 + gsi;
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irq = gsi_top + gsi;
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return irq;
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}
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@@ -129,10 +129,10 @@ static u32 irq_to_gsi(int irq)
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if (irq < NR_IRQS_LEGACY)
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gsi = isa_irq_to_gsi[irq];
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else if (irq <= gsi_end)
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else if (irq < gsi_top)
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gsi = irq;
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else if (irq <= (gsi_end + NR_IRQS_LEGACY))
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gsi = irq - gsi_end;
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else if (irq < (gsi_top + NR_IRQS_LEGACY))
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gsi = irq - gsi_top;
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else
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gsi = 0xffffffff;
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@@ -89,8 +89,8 @@ int nr_ioapics;
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/* IO APIC gsi routing info */
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struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
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/* The last gsi number used */
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u32 gsi_end;
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/* The one past the highest gsi number used */
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u32 gsi_top;
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/* MP IRQ source entries */
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struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
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@@ -1035,7 +1035,7 @@ static int pin_2_irq(int idx, int apic, int pin)
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if (gsi >= NR_IRQS_LEGACY)
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irq = gsi;
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else
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irq = gsi_end + 1 + gsi;
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irq = gsi_top + gsi;
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}
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#ifdef CONFIG_X86_32
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@@ -3853,7 +3853,7 @@ void __init probe_nr_irqs_gsi(void)
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{
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int nr;
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nr = gsi_end + 1 + NR_IRQS_LEGACY;
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nr = gsi_top + NR_IRQS_LEGACY;
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if (nr > nr_irqs_gsi)
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nr_irqs_gsi = nr;
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@@ -4294,8 +4294,8 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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*/
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nr_ioapic_registers[idx] = entries;
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if (mp_gsi_routing[idx].gsi_end > gsi_end)
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gsi_end = mp_gsi_routing[idx].gsi_end;
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if (mp_gsi_routing[idx].gsi_end >= gsi_top)
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gsi_top = mp_gsi_routing[idx].gsi_end + 1;
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printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
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"GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
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@@ -72,6 +72,7 @@ static struct event_constraint intel_westmere_event_constraints[] =
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
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EVENT_CONSTRAINT_END
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};
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@@ -729,7 +729,7 @@ static int __init e820_mark_nvs_memory(void)
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struct e820entry *ei = &e820.map[i];
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if (ei->type == E820_NVS)
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hibernate_nvs_register(ei->addr, ei->size);
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suspend_nvs_register(ei->addr, ei->size);
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}
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return 0;
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@@ -123,7 +123,7 @@ static void __init MP_ioapic_info(struct mpc_ioapic *m)
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printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
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m->apicid, m->apicver, m->apicaddr);
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mp_register_ioapic(m->apicid, m->apicaddr, gsi_end + 1);
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mp_register_ioapic(m->apicid, m->apicaddr, gsi_top);
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}
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static void print_MP_intsrc_info(struct mpc_intsrc *m)
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@@ -103,11 +103,16 @@ int use_calgary __read_mostly = 0;
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#define PMR_SOFTSTOPFAULT 0x40000000
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#define PMR_HARDSTOP 0x20000000
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#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
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#define MAX_NUM_CHASSIS 8 /* max number of chassis */
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/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
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#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
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#define PHBS_PER_CALGARY 4
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/*
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* The maximum PHB bus number.
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* x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
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* x3950M2: 4 chassis, 48 PHBs per chassis = 192
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* x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
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* x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
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*/
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#define MAX_PHB_BUS_NUM 384
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#define PHBS_PER_CALGARY 4
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/* register offsets in Calgary's internal register space */
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static const unsigned long tar_offsets[] = {
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@@ -228,6 +228,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
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DMI_MATCH(DMI_PRODUCT_NAME, "Precision WorkStation T5400"),
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},
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},
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{ /* Handle problems with rebooting on Dell T7400's */
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.callback = set_bios_reboot,
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.ident = "Dell Precision T7400",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Precision WorkStation T7400"),
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},
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},
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{ /* Handle problems with rebooting on HP laptops */
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.callback = set_bios_reboot,
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.ident = "HP Compaq Laptop",
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@@ -93,7 +93,7 @@ static int __init sfi_parse_ioapic(struct sfi_table_header *table)
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pentry = (struct sfi_apic_table_entry *)sb->pentry;
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for (i = 0; i < num; i++) {
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mp_register_ioapic(i, pentry->phys_addr, gsi_end + 1);
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mp_register_ioapic(i, pentry->phys_addr, gsi_top);
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pentry++;
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}
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