cxl: Add psl9 specific code
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translation Fault Handling
- CAPP
- Memory Context ID
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
[mpe: Fixup comment formatting, unsplit long strings]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Lombard
committato da
Michael Ellerman
Michael Ellerman
parent
abd1d99bb3
commit
f24be42aab
@@ -120,6 +120,7 @@ int cxl_psl_purge(struct cxl_afu *afu)
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u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
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u64 dsisr, dar;
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u64 start, end;
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u64 trans_fault = 0x0ULL;
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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int rc = 0;
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@@ -127,6 +128,11 @@ int cxl_psl_purge(struct cxl_afu *afu)
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pr_devel("PSL purge request\n");
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if (cxl_is_psl8(afu))
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trans_fault = CXL_PSL_DSISR_TRANS;
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if (cxl_is_psl9(afu))
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trans_fault = CXL_PSL9_DSISR_An_TF;
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if (!cxl_ops->link_ok(afu->adapter, afu)) {
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dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
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rc = -EIO;
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@@ -158,7 +164,7 @@ int cxl_psl_purge(struct cxl_afu *afu)
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pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n",
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PSL_CNTL, dsisr);
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if (dsisr & CXL_PSL_DSISR_TRANS) {
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if (dsisr & trans_fault) {
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dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
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dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n",
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dsisr, dar);
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@@ -200,7 +206,7 @@ static int spa_max_procs(int spa_size)
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return ((spa_size / 8) - 96) / 17;
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}
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int cxl_alloc_spa(struct cxl_afu *afu)
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static int cxl_alloc_spa(struct cxl_afu *afu, int mode)
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{
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unsigned spa_size;
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@@ -213,7 +219,8 @@ int cxl_alloc_spa(struct cxl_afu *afu)
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if (spa_size > 0x100000) {
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dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
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afu->native->spa_max_procs, afu->native->spa_size);
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afu->num_procs = afu->native->spa_max_procs;
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if (mode != CXL_MODE_DEDICATED)
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afu->num_procs = afu->native->spa_max_procs;
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break;
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}
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@@ -262,6 +269,36 @@ void cxl_release_spa(struct cxl_afu *afu)
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}
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}
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/*
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* Invalidation of all ERAT entries is no longer required by CAIA2. Use
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* only for debug.
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*/
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int cxl_invalidate_all_psl9(struct cxl *adapter)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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u64 ierat;
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pr_devel("CXL adapter - invalidation of all ERAT entries\n");
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/* Invalidates all ERAT entries for Radix or HPT */
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ierat = CXL_XSL9_IERAT_IALL;
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if (radix_enabled())
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ierat |= CXL_XSL9_IERAT_INVR;
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cxl_p1_write(adapter, CXL_XSL9_IERAT, ierat);
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while (cxl_p1_read(adapter, CXL_XSL9_IERAT) & CXL_XSL9_IERAT_IINPROG) {
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if (time_after_eq(jiffies, timeout)) {
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dev_warn(&adapter->dev,
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"WARNING: CXL adapter invalidation of all ERAT entries timed out!\n");
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return -EBUSY;
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}
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if (!cxl_ops->link_ok(adapter, NULL))
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return -EIO;
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cpu_relax();
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}
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return 0;
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}
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int cxl_invalidate_all_psl8(struct cxl *adapter)
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{
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unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
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@@ -498,7 +535,7 @@ static int activate_afu_directed(struct cxl_afu *afu)
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afu->num_procs = afu->max_procs_virtualised;
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if (afu->native->spa == NULL) {
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if (cxl_alloc_spa(afu))
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if (cxl_alloc_spa(afu, CXL_MODE_DIRECTED))
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return -ENOMEM;
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}
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attach_spa(afu);
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@@ -548,10 +585,19 @@ static u64 calculate_sr(struct cxl_context *ctx)
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sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
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} else {
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sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
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sr &= ~(CXL_PSL_SR_An_HV);
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if (radix_enabled())
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sr |= CXL_PSL_SR_An_HV;
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else
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sr &= ~(CXL_PSL_SR_An_HV);
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if (!test_tsk_thread_flag(current, TIF_32BIT))
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sr |= CXL_PSL_SR_An_SF;
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}
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if (cxl_is_psl9(ctx->afu)) {
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if (radix_enabled())
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sr |= CXL_PSL_SR_An_XLAT_ror;
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else
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sr |= CXL_PSL_SR_An_XLAT_hpt;
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}
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return sr;
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}
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@@ -584,6 +630,70 @@ static void update_ivtes_directed(struct cxl_context *ctx)
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WARN_ON(add_process_element(ctx));
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}
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static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
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{
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u32 pid;
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cxl_assign_psn_space(ctx);
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ctx->elem->ctxtime = 0; /* disable */
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ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
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ctx->elem->haurp = 0; /* disable */
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if (ctx->kernel)
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pid = 0;
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else {
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if (ctx->mm == NULL) {
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pr_devel("%s: unable to get mm for pe=%d pid=%i\n",
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__func__, ctx->pe, pid_nr(ctx->pid));
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return -EINVAL;
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}
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pid = ctx->mm->context.id;
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}
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ctx->elem->common.tid = 0;
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ctx->elem->common.pid = cpu_to_be32(pid);
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ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
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ctx->elem->common.csrp = 0; /* disable */
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cxl_prefault(ctx, wed);
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/*
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* Ensure we have the multiplexed PSL interrupt set up to take faults
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* for kernel contexts that may not have allocated any AFU IRQs at all:
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*/
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if (ctx->irqs.range[0] == 0) {
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ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
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ctx->irqs.range[0] = 1;
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}
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ctx->elem->common.amr = cpu_to_be64(amr);
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ctx->elem->common.wed = cpu_to_be64(wed);
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return 0;
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}
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int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
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{
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int result;
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/* fill the process element entry */
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result = process_element_entry_psl9(ctx, wed, amr);
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if (result)
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return result;
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update_ivtes_directed(ctx);
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/* first guy needs to enable */
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result = cxl_ops->afu_check_and_enable(ctx->afu);
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if (result)
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return result;
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return add_process_element(ctx);
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}
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int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
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{
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u32 pid;
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@@ -594,7 +704,7 @@ int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
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ctx->elem->ctxtime = 0; /* disable */
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ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
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ctx->elem->haurp = 0; /* disable */
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ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
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ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1));
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pid = current->pid;
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if (ctx->kernel)
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@@ -605,13 +715,13 @@ int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
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ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
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ctx->elem->common.csrp = 0; /* disable */
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ctx->elem->common.aurp0 = 0; /* disable */
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ctx->elem->common.aurp1 = 0; /* disable */
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ctx->elem->common.u.psl8.aurp0 = 0; /* disable */
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ctx->elem->common.u.psl8.aurp1 = 0; /* disable */
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cxl_prefault(ctx, wed);
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ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
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ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
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ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
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ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
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/*
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* Ensure we have the multiplexed PSL interrupt set up to take faults
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@@ -677,6 +787,32 @@ static int deactivate_afu_directed(struct cxl_afu *afu)
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return 0;
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}
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int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu)
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{
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dev_info(&afu->dev, "Activating dedicated process mode\n");
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/*
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* If XSL is set to dedicated mode (Set in PSL_SCNTL reg), the
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* XSL and AFU are programmed to work with a single context.
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* The context information should be configured in the SPA area
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* index 0 (so PSL_SPAP must be configured before enabling the
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* AFU).
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*/
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afu->num_procs = 1;
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if (afu->native->spa == NULL) {
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if (cxl_alloc_spa(afu, CXL_MODE_DEDICATED))
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return -ENOMEM;
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}
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attach_spa(afu);
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cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
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cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
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afu->current_mode = CXL_MODE_DEDICATED;
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return cxl_chardev_d_afu_add(afu);
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}
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int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
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{
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dev_info(&afu->dev, "Activating dedicated process mode\n");
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@@ -700,6 +836,16 @@ int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
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return cxl_chardev_d_afu_add(afu);
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}
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void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx)
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{
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int r;
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for (r = 0; r < CXL_IRQ_RANGES; r++) {
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ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
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ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
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}
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}
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void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
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{
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struct cxl_afu *afu = ctx->afu;
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@@ -716,6 +862,26 @@ void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
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((u64)ctx->irqs.range[3] & 0xffff));
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}
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int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
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{
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struct cxl_afu *afu = ctx->afu;
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int result;
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/* fill the process element entry */
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result = process_element_entry_psl9(ctx, wed, amr);
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if (result)
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return result;
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if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
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afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
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result = cxl_ops->afu_reset(afu);
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if (result)
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return result;
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return afu_enable(afu);
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}
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int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
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{
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struct cxl_afu *afu = ctx->afu;
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@@ -887,6 +1053,21 @@ static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
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return 0;
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}
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void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
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{
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u64 fir1, fir2, serr;
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fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
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fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR2);
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dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
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dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
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if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
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serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
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cxl_afu_decode_psl_serr(ctx->afu, serr);
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}
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}
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void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
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{
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u64 fir1, fir2, fir_slice, serr, afu_debug;
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@@ -923,9 +1104,20 @@ static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
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return cxl_ops->ack_irq(ctx, 0, errstat);
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}
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static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr)
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{
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if ((cxl_is_psl8(afu)) && (dsisr & CXL_PSL_DSISR_TRANS))
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return true;
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if ((cxl_is_psl9(afu)) && (dsisr & CXL_PSL9_DSISR_An_TF))
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return true;
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return false;
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}
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irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
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{
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if (irq_info->dsisr & CXL_PSL_DSISR_TRANS)
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if (cxl_is_translation_fault(afu, irq_info->dsisr))
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
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else
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
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@@ -994,6 +1186,9 @@ static void native_irq_wait(struct cxl_context *ctx)
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if (cxl_is_psl8(ctx->afu) &&
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((dsisr & CXL_PSL_DSISR_PENDING) == 0))
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return;
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if (cxl_is_psl9(ctx->afu) &&
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((dsisr & CXL_PSL9_DSISR_PENDING) == 0))
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return;
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/*
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* We are waiting for the workqueue to process our
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* irq, so need to let that run here.
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@@ -1122,6 +1317,13 @@ int cxl_native_register_serr_irq(struct cxl_afu *afu)
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serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
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if (cxl_is_power8())
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serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
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if (cxl_is_power9()) {
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/*
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* By default, all errors are masked. So don't set all masks.
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* Slice errors will be transfered.
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*/
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serr = (serr & ~0xff0000007fffffffULL) | (afu->serr_hwirq & 0xffff);
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}
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cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
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return 0;
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