[POWERPC] Remove the dregs of APUS support from arch/powerpc
APUS (the Amiga Power-Up System) is not supported under arch/powerpc and it's unlikely it ever will be. Therefore, this patch removes the fragments of APUS support code from arch/powerpc which have been copied from arch/ppc. A few APUS references are left in asm-powerpc in .h files which are still used from arch/ppc. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson
committed by
Paul Mackerras
Paul Mackerras
parent
90ac19a8b2
commit
f21f49ea63
@@ -9,7 +9,6 @@
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
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*
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* This file contains the low-level support and setup for the
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* PowerPC platform, including trap and interrupt dispatch.
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@@ -32,10 +31,6 @@
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_APUS
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#include <asm/amigappc.h>
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#endif
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/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
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#define LOAD_BAT(n, reg, RA, RB) \
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/* see the comment for clear_bats() -- Cort */ \
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@@ -92,11 +87,6 @@ _start:
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* r4: virtual address of boot_infos_t
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* r5: 0
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*
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* APUS
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* r3: 'APUS'
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* r4: physical address of memory base
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* Linux/m68k style BootInfo structure at &_end.
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*
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* PREP
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* This is jumped to on prep systems right after the kernel is relocated
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* to its proper place in memory by the boot loader. The expected layout
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@@ -150,14 +140,6 @@ __start:
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*/
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bl early_init
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#ifdef CONFIG_APUS
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/* On APUS the __va/__pa constants need to be set to the correct
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* values before continuing.
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*/
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mr r4,r30
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bl fix_mem_constants
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#endif /* CONFIG_APUS */
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/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
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* the physical address we are running at, returned by early_init()
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*/
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@@ -167,7 +149,7 @@ __after_mmu_off:
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bl flush_tlbs
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bl initial_bats
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#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
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#if defined(CONFIG_BOOTX_TEXT)
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bl setup_disp_bat
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#endif
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@@ -183,7 +165,6 @@ __after_mmu_off:
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#endif /* CONFIG_6xx */
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#ifndef CONFIG_APUS
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/*
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* We need to run with _start at physical address 0.
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* On CHRP, we are loaded at 0x10000 since OF on CHRP uses
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@@ -196,7 +177,6 @@ __after_mmu_off:
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addis r4,r3,KERNELBASE@h /* current address of _start */
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cmpwi 0,r4,0 /* are we already running at 0? */
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bne relocate_kernel
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#endif /* CONFIG_APUS */
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/*
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* we now have the 1st 16M of ram mapped with the bats.
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* prep needs the mmu to be turned on here, but pmac already has it on.
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@@ -881,85 +861,6 @@ _GLOBAL(copy_and_flush)
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addi r6,r6,4
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blr
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#ifdef CONFIG_APUS
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/*
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* On APUS the physical base address of the kernel is not known at compile
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* time, which means the __pa/__va constants used are incorrect. In the
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* __init section is recorded the virtual addresses of instructions using
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* these constants, so all that has to be done is fix these before
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* continuing the kernel boot.
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*
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* r4 = The physical address of the kernel base.
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*/
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fix_mem_constants:
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mr r10,r4
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addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
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neg r11,r10 /* phys_to_virt constant */
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lis r12,__vtop_table_begin@h
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ori r12,r12,__vtop_table_begin@l
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add r12,r12,r10 /* table begin phys address */
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lis r13,__vtop_table_end@h
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ori r13,r13,__vtop_table_end@l
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add r13,r13,r10 /* table end phys address */
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subi r12,r12,4
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subi r13,r13,4
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1: lwzu r14,4(r12) /* virt address of instruction */
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add r14,r14,r10 /* phys address of instruction */
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lwz r15,0(r14) /* instruction, now insert top */
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rlwimi r15,r10,16,16,31 /* half of vp const in low half */
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stw r15,0(r14) /* of instruction and restore. */
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dcbst r0,r14 /* write it to memory */
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sync
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icbi r0,r14 /* flush the icache line */
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cmpw r12,r13
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bne 1b
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sync /* additional sync needed on g4 */
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isync
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/*
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* Map the memory where the exception handlers will
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* be copied to when hash constants have been patched.
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*/
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#ifdef CONFIG_APUS_FAST_EXCEPT
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lis r8,0xfff0
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#else
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lis r8,0
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#endif
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ori r8,r8,0x2 /* 128KB, supervisor */
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mtspr SPRN_DBAT3U,r8
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mtspr SPRN_DBAT3L,r8
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lis r12,__ptov_table_begin@h
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ori r12,r12,__ptov_table_begin@l
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add r12,r12,r10 /* table begin phys address */
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lis r13,__ptov_table_end@h
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ori r13,r13,__ptov_table_end@l
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add r13,r13,r10 /* table end phys address */
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subi r12,r12,4
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subi r13,r13,4
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1: lwzu r14,4(r12) /* virt address of instruction */
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add r14,r14,r10 /* phys address of instruction */
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lwz r15,0(r14) /* instruction, now insert top */
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rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
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stw r15,0(r14) /* of instruction and restore. */
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dcbst r0,r14 /* write it to memory */
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sync
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icbi r0,r14 /* flush the icache line */
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cmpw r12,r13
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bne 1b
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sync /* additional sync needed on g4 */
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isync /* No speculative loading until now */
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blr
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/***********************************************************************
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* Please note that on APUS the exception handlers are located at the
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* physical address 0xfff0000. For this reason, the exception handlers
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* cannot use relative branches to access the code below.
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***********************************************************************/
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#endif /* CONFIG_APUS */
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#ifdef CONFIG_SMP
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#ifdef CONFIG_GEMINI
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.globl __secondary_start_gemini
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@@ -1135,19 +1036,6 @@ start_here:
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bl __save_cpu_setup
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bl MMU_init
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#ifdef CONFIG_APUS
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/* Copy exception code to exception vector base on APUS. */
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lis r4,KERNELBASE@h
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#ifdef CONFIG_APUS_FAST_EXCEPT
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lis r3,0xfff0 /* Copy to 0xfff00000 */
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#else
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lis r3,0 /* Copy to 0x00000000 */
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#endif
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li r5,0x4000 /* # bytes of memory to copy */
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li r6,0
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bl copy_and_flush /* copy the first 0x4000 bytes */
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#endif /* CONFIG_APUS */
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/*
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* Go back to running unmapped so we can load up new values
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* for SDR1 (hash table pointer) and the segment registers
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@@ -1324,11 +1212,7 @@ initial_bats:
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#else
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ori r8,r8,2 /* R/W access */
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_APUS
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ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
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#else
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ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
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#endif /* CONFIG_APUS */
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mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
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mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
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@@ -1338,7 +1222,7 @@ initial_bats:
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blr
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#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
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#ifdef CONFIG_BOOTX_TEXT
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setup_disp_bat:
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/*
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* setup the display bat prepared for us in prom.c
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@@ -1362,7 +1246,7 @@ setup_disp_bat:
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1: mtspr SPRN_IBAT3L,r8
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mtspr SPRN_IBAT3U,r11
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blr
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#endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
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#endif /* CONFIG_BOOTX_TEXT */
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#ifdef CONFIG_8260
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/* Jump into the system reset for the rom.
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