xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sh: migrate to arch/sh/include/

Browse Source 
This follows the sparc changes a439fe51a1.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
2008-07-29 08:09:44 +09:00
parent 25326277d8
commit f15cbe6f1a
296 changed files with 268 additions and 131 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
arch/sh/include/cpu-sh2/cpu/addrspace.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* Definitions for the address spaces of the SH-2 CPUs.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_ADDRSPACE_H
#define __ASM_CPU_SH2_ADDRSPACE_H
#define P0SEG 0x00000000
#define P1SEG 0x80000000
#define P2SEG 0xa0000000
#define P3SEG 0xc0000000
#define P4SEG 0xe0000000
#endif /* __ASM_CPU_SH2_ADDRSPACE_H */

41
arch/sh/include/cpu-sh2/cpu/cache.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* include/asm-sh/cpu-sh2/cache.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_CACHE_H
#define __ASM_CPU_SH2_CACHE_H
#define L1_CACHE_SHIFT 4
#define SH_CACHE_VALID 1
#define SH_CACHE_UPDATED 2
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define CCR 0xffffffec
#define CCR_CACHE_CE 0x01 /* Cache enable */
#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
/* 0x00000000-0x7fffffff: Write-through */
/* 0x80000000-0x9fffffff: Write-back */
/* 0xc0000000-0xdfffffff: Write-through */
#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
/* 0x00000000-0x7fffffff: Write-back */
/* 0x80000000-0x9fffffff: Write-through */
/* 0xc0000000-0xdfffffff: Write-back */
#define CCR_CACHE_CF 0x08 /* Cache invalidate */
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_DATA_ARRAY 0xf1000000
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#endif
#endif /* __ASM_CPU_SH2_CACHE_H */

44
arch/sh/include/cpu-sh2/cpu/cacheflush.h Normal file
View File

@@ -0,0 +1,44 @@
/*
* include/asm-sh/cpu-sh2/cacheflush.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
#define __ASM_CPU_SH2_CACHEFLUSH_H
/*
* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_dup mm(mm) handles cache flushing when forking
* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
*
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
* - flush_icache_range(start, end) flushes(invalidates) a range for icache
* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
*
* Caches are indexed (effectively) by physical address on SH-2, so
* we don't need them.
*/
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define p3_cache_init() do { } while (0)
#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */

23
arch/sh/include/cpu-sh2/cpu/dma.h Normal file
View File

@@ -0,0 +1,23 @@
/*
* Definitions for the SH-2 DMAC.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_DMA_H
#define __ASM_CPU_SH2_DMA_H
#define SH_MAX_DMA_CHANNELS 2
#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
#define DMAOR 0xffffffb0
#endif /* __ASM_CPU_SH2_DMA_H */

18
arch/sh/include/cpu-sh2/cpu/freq.h Normal file
View File

@@ -0,0 +1,18 @@
/*
* include/asm-sh/cpu-sh2/freq.h
*
* Copyright (C) 2006 Yoshinori Sato
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_FREQ_H
#define __ASM_CPU_SH2_FREQ_H
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define FREQCR 0xf815ff80
#endif
#endif /* __ASM_CPU_SH2_FREQ_H */

16
arch/sh/include/cpu-sh2/cpu/mmu_context.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* include/asm-sh/cpu-sh2/mmu_context.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
#define __ASM_CPU_SH2_MMU_CONTEXT_H
/* No MMU */
#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */

8
arch/sh/include/cpu-sh2/cpu/rtc.h Normal file
View File

@@ -0,0 +1,8 @@
#ifndef __ASM_SH_CPU_SH2_RTC_H
#define __ASM_SH_CPU_SH2_RTC_H
#define rtc_reg_size sizeof(u16)
#define RTC_BIT_INVERTED 0
#define RTC_DEF_CAPABILITIES 0UL
#endif /* __ASM_SH_CPU_SH2_RTC_H */

17
arch/sh/include/cpu-sh2/cpu/sigcontext.h Normal file
View File

@@ -0,0 +1,17 @@
#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
#define __ASM_CPU_SH2_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
};
#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */

6
arch/sh/include/cpu-sh2/cpu/timer.h Normal file
View File

@@ -0,0 +1,6 @@
#ifndef __ASM_CPU_SH2_TIMER_H
#define __ASM_CPU_SH2_TIMER_H
/* Nothing needed yet */
#endif /* __ASM_CPU_SH2_TIMER_H */

32
arch/sh/include/cpu-sh2/cpu/ubc.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* include/asm-sh/cpu-sh2/ubc.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_UBC_H
#define __ASM_CPU_SH2_UBC_H
#define UBC_BARA 0xffffff40
#define UBC_BAMRA 0xffffff44
#define UBC_BBRA 0xffffff48
#define UBC_BARB 0xffffff60
#define UBC_BAMRB 0xffffff64
#define UBC_BBRB 0xffffff68
#define UBC_BDRB 0xffffff70
#define UBC_BDMRB 0xffffff74
#define UBC_BRCR 0xffffff78
/*
* We don't have any ASID changes to make in the UBC on the SH-2.
*
* Make these purposely invalid to track misuse.
*/
#define UBC_BASRA 0x00000000
#define UBC_BASRB 0x00000000
#endif /* __ASM_CPU_SH2_UBC_H */

69
arch/sh/include/cpu-sh2/cpu/watchdog.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* include/asm-sh/cpu-sh2/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_WATCHDOG_H
#define __ASM_CPU_SH2_WATCHDOG_H
/*
* More SH-2 brilliance .. its not good enough that we can't read
* and write the same sizes to WTCNT, now we have to read and write
* with different sizes at different addresses for WTCNT _and_ RSTCSR.
*
* At least on the bright side no one has managed to screw over WTCSR
* in this fashion .. yet.
*/
/* Register definitions */
#define WTCNT 0xfffffe80
#define WTCSR 0xfffffe80
#define RSTCSR 0xfffffe82
#define WTCNT_R (WTCNT + 1)
#define RSTCSR_R (RSTCSR + 1)
/* Bit definitions */
#define WTCSR_IOVF 0x80
#define WTCSR_WT 0x40
#define WTCSR_TME 0x20
#define WTCSR_RSTS 0x00
#define RSTCSR_RSTS 0x20
/**
* sh_wdt_read_rstcsr - Read from Reset Control/Status Register
*
* Reads back the RSTCSR value.
*/
static inline __u8 sh_wdt_read_rstcsr(void)
{
/*
* Same read/write brain-damage as for WTCNT here..
*/
return ctrl_inb(RSTCSR_R);
}
/**
* sh_wdt_write_csr - Write to Reset Control/Status Register
*
* @val: Value to write
*
* Writes the given value @val to the lower byte of the control/status
* register. The upper byte is set manually on each write.
*/
static inline void sh_wdt_write_rstcsr(__u8 val)
{
/*
* Note: Due to the brain-damaged nature of this register,
* we can't presently touch the WOVF bit, since the upper byte
* has to be swapped for this. So just leave it alone..
*/
ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
}
#endif /* __ASM_CPU_SH2_WATCHDOG_H */