[PATCH] I2O: new sysfs attributes and Adaptec specific block device access and 64-bit DMA support
Changes: - Added Bus-OSM which could be used by user space programs to reset a channel on the controller - Make ioctl's in Config-OSM obsolete in prefer for sysfs attributes and move those to its own file - Added sysfs attribute for firmware read and write access for I2O controllers - Added special handling of firmware read and write access for Adaptec controllers - Added vendor id and product id as sysfs-attribute to Executive classes - Added automatic notification of LCT change handling to Exec-OSM - Added flushing function to Block-OSM for later barrier implementation - Use PRIVATE messages for Block access on Adaptec controllers, which are faster then BLOCK class access - Cleaned up support for Promise controller - New messages are now detected using the IRQ status register as suggested by the I2O spec - Added i2o_dma_high() and i2o_dma_low() functions - Added facility for SG tablesize calculation when using 32-bit and 64-bit DMA addresses - Added i2o_dma_map_single() and i2o_dma_map_sg() which could build the SG list for 32-bit as well as 64-bit DMA addresses Signed-off-by: Markus Lidel <Markus.Lidel@shadowconnect.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Markus Lidel
committed by
Linus Torvalds
Linus Torvalds
parent
f88e119c4b
commit
f10378fff6
@@ -32,6 +32,10 @@ typedef unsigned int u32;
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#endif /* __KERNEL__ */
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/*
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* Vendors
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*/
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#define I2O_VENDOR_DPT 0x001b
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/*
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* I2O Control IOCTLs and structures
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@@ -333,7 +337,7 @@ typedef struct _i2o_status_block {
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#define I2O_CLASS_ATE_PERIPHERAL 0x061
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#define I2O_CLASS_FLOPPY_CONTROLLER 0x070
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#define I2O_CLASS_FLOPPY_DEVICE 0x071
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#define I2O_CLASS_BUS_ADAPTER_PORT 0x080
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#define I2O_CLASS_BUS_ADAPTER 0x080
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#define I2O_CLASS_PEER_TRANSPORT_AGENT 0x090
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#define I2O_CLASS_PEER_TRANSPORT 0x091
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#define I2O_CLASS_END 0xfff
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@@ -157,7 +157,8 @@ struct i2o_controller {
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void __iomem *in_port; /* Inbout port address */
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void __iomem *out_port; /* Outbound port address */
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void __iomem *irq_mask; /* Interrupt register address */
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void __iomem *irq_status; /* Interrupt status register address */
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void __iomem *irq_mask; /* Interrupt mask register address */
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/* Dynamic LCT related data */
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@@ -242,15 +243,6 @@ extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
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extern void i2o_msg_nop(struct i2o_controller *, u32);
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static inline void i2o_flush_reply(struct i2o_controller *, u32);
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/* DMA handling functions */
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static inline int i2o_dma_alloc(struct device *, struct i2o_dma *, size_t,
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unsigned int);
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static inline void i2o_dma_free(struct device *, struct i2o_dma *);
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int i2o_dma_realloc(struct device *, struct i2o_dma *, size_t, unsigned int);
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static inline int i2o_dma_map(struct device *, struct i2o_dma *);
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static inline void i2o_dma_unmap(struct device *, struct i2o_dma *);
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/* IOP functions */
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extern int i2o_status_get(struct i2o_controller *);
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@@ -275,6 +267,16 @@ static inline u32 i2o_ptr_high(void *ptr)
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{
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return (u32) ((u64) ptr >> 32);
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};
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static inline u32 i2o_dma_low(dma_addr_t dma_addr)
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{
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return (u32) (u64) dma_addr;
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};
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static inline u32 i2o_dma_high(dma_addr_t dma_addr)
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{
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return (u32) ((u64) dma_addr >> 32);
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};
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#else
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static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
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{
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@@ -305,8 +307,246 @@ static inline u32 i2o_ptr_high(void *ptr)
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{
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return 0;
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};
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static inline u32 i2o_dma_low(dma_addr_t dma_addr)
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{
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return (u32) dma_addr;
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};
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static inline u32 i2o_dma_high(dma_addr_t dma_addr)
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{
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return 0;
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};
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#endif
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/**
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* i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
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* @c: I2O controller for which the calculation should be done
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* @body_size: maximum body size used for message in 32-bit words.
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*
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* Return the maximum number of SG elements in a SG list.
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*/
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static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
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{
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i2o_status_block *sb = c->status_block.virt;
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u16 sg_count =
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(sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
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body_size;
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if (c->pae_support) {
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/*
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* for 64-bit a SG attribute element must be added and each
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* SG element needs 12 bytes instead of 8.
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*/
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sg_count -= 2;
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sg_count /= 3;
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} else
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sg_count /= 2;
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if (c->short_req && (sg_count > 8))
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sg_count = 8;
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return sg_count;
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};
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/**
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* i2o_dma_map_single - Map pointer to controller and fill in I2O message.
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* @c: I2O controller
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* @ptr: pointer to the data which should be mapped
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* @size: size of data in bytes
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* @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
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* @sg_ptr: pointer to the SG list inside the I2O message
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*
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* This function does all necessary DMA handling and also writes the I2O
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* SGL elements into the I2O message. For details on DMA handling see also
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* dma_map_single(). The pointer sg_ptr will only be set to the end of the
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* SG list if the allocation was successful.
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*
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* Returns DMA address which must be checked for failures using
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* dma_mapping_error().
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*/
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static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
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size_t size,
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enum dma_data_direction direction,
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u32 __iomem ** sg_ptr)
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{
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u32 sg_flags;
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u32 __iomem *mptr = *sg_ptr;
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dma_addr_t dma_addr;
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switch (direction) {
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case DMA_TO_DEVICE:
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sg_flags = 0xd4000000;
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break;
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case DMA_FROM_DEVICE:
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sg_flags = 0xd0000000;
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break;
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default:
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return 0;
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}
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dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
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if (!dma_mapping_error(dma_addr)) {
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
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writel(0x7C020002, mptr++);
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writel(PAGE_SIZE, mptr++);
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}
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#endif
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writel(sg_flags | size, mptr++);
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writel(i2o_dma_low(dma_addr), mptr++);
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support)
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writel(i2o_dma_high(dma_addr), mptr++);
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#endif
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*sg_ptr = mptr;
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}
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return dma_addr;
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};
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/**
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* i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
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* @c: I2O controller
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* @sg: SG list to be mapped
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* @sg_count: number of elements in the SG list
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* @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
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* @sg_ptr: pointer to the SG list inside the I2O message
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*
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* This function does all necessary DMA handling and also writes the I2O
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* SGL elements into the I2O message. For details on DMA handling see also
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* dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
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* list if the allocation was successful.
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*
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* Returns 0 on failure or 1 on success.
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*/
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static inline int i2o_dma_map_sg(struct i2o_controller *c,
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struct scatterlist *sg, int sg_count,
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enum dma_data_direction direction,
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u32 __iomem ** sg_ptr)
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{
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u32 sg_flags;
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u32 __iomem *mptr = *sg_ptr;
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switch (direction) {
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case DMA_TO_DEVICE:
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sg_flags = 0x14000000;
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break;
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case DMA_FROM_DEVICE:
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sg_flags = 0x10000000;
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break;
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default:
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return 0;
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}
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sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
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if (!sg_count)
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return 0;
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
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writel(0x7C020002, mptr++);
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writel(PAGE_SIZE, mptr++);
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}
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#endif
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while (sg_count-- > 0) {
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if (!sg_count)
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sg_flags |= 0xC0000000;
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writel(sg_flags | sg_dma_len(sg), mptr++);
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writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
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#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
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if ((sizeof(dma_addr_t) > 4) && c->pae_support)
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writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
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#endif
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sg++;
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}
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*sg_ptr = mptr;
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return 1;
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};
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/**
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* i2o_dma_alloc - Allocate DMA memory
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* @dev: struct device pointer to the PCI device of the I2O controller
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* @addr: i2o_dma struct which should get the DMA buffer
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* @len: length of the new DMA memory
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* @gfp_mask: GFP mask
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*
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* Allocate a coherent DMA memory and write the pointers into addr.
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*
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* Returns 0 on success or -ENOMEM on failure.
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*/
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static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
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size_t len, unsigned int gfp_mask)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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int dma_64 = 0;
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if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
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dma_64 = 1;
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if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
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return -ENOMEM;
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}
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addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
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if ((sizeof(dma_addr_t) > 4) && dma_64)
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if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
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printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
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if (!addr->virt)
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return -ENOMEM;
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memset(addr->virt, 0, len);
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addr->len = len;
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return 0;
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};
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/**
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* i2o_dma_free - Free DMA memory
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* @dev: struct device pointer to the PCI device of the I2O controller
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* @addr: i2o_dma struct which contains the DMA buffer
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*
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* Free a coherent DMA memory and set virtual address of addr to NULL.
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*/
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static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
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{
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if (addr->virt) {
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if (addr->phys)
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dma_free_coherent(dev, addr->len, addr->virt,
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addr->phys);
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else
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kfree(addr->virt);
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addr->virt = NULL;
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}
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};
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/**
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* i2o_dma_realloc - Realloc DMA memory
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* @dev: struct device pointer to the PCI device of the I2O controller
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* @addr: pointer to a i2o_dma struct DMA buffer
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* @len: new length of memory
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* @gfp_mask: GFP mask
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*
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* If there was something allocated in the addr, free it first. If len > 0
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* than try to allocate it and write the addresses back to the addr
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* structure. If len == 0 set the virtual address to NULL.
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*
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* Returns the 0 on success or negative error code on failure.
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*/
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static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
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size_t len, unsigned int gfp_mask)
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{
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i2o_dma_free(dev, addr);
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if (len)
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return i2o_dma_alloc(dev, addr, len, gfp_mask);
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return 0;
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};
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/* I2O driver (OSM) functions */
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extern int i2o_driver_register(struct i2o_driver *);
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extern void i2o_driver_unregister(struct i2o_driver *);
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@@ -375,10 +615,11 @@ extern int i2o_device_claim_release(struct i2o_device *);
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/* Exec OSM functions */
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extern int i2o_exec_lct_get(struct i2o_controller *);
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/* device / driver conversion functions */
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/* device / driver / kobject conversion functions */
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#define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
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#define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
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#define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
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#define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
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/**
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* i2o_msg_get - obtain an I2O message from the IOP
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@@ -466,8 +707,10 @@ static inline struct i2o_message __iomem *i2o_msg_out_to_virt(struct
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i2o_controller *c,
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u32 m)
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{
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BUG_ON(m < c->out_queue.phys
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|| m >= c->out_queue.phys + c->out_queue.len);
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if (unlikely
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(m < c->out_queue.phys
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|| m >= c->out_queue.phys + c->out_queue.len))
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return NULL;
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return c->out_queue.virt + (m - c->out_queue.phys);
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};
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@@ -532,48 +775,6 @@ static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
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}
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};
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/**
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* i2o_dma_map - Map the memory to DMA
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* @dev: struct device pointer to the PCI device of the I2O controller
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* @addr: i2o_dma struct which should be mapped
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*
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* Map the memory in addr->virt to coherent DMA memory and write the
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* physical address into addr->phys.
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*
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* Returns 0 on success or -ENOMEM on failure.
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*/
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static inline int i2o_dma_map(struct device *dev, struct i2o_dma *addr)
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{
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if (!addr->virt)
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return -EFAULT;
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if (!addr->phys)
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addr->phys = dma_map_single(dev, addr->virt, addr->len,
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DMA_BIDIRECTIONAL);
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if (!addr->phys)
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return -ENOMEM;
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return 0;
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};
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/**
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* i2o_dma_unmap - Unmap the DMA memory
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* @dev: struct device pointer to the PCI device of the I2O controller
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* @addr: i2o_dma struct which should be unmapped
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*
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* Unmap the memory in addr->virt from DMA memory.
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*/
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static inline void i2o_dma_unmap(struct device *dev, struct i2o_dma *addr)
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{
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if (!addr->virt)
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return;
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if (addr->phys) {
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dma_unmap_single(dev, addr->phys, addr->len, DMA_BIDIRECTIONAL);
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addr->phys = 0;
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}
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};
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/*
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* Endian handling wrapped into the macro - keeps the core code
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* cleaner.
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@@ -725,6 +926,14 @@ extern void i2o_debug_state(struct i2o_controller *c);
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#define I2O_CMD_SCSI_ABORT 0x83
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#define I2O_CMD_SCSI_BUSRESET 0x27
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/*
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* Bus Adapter Class
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*/
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#define I2O_CMD_BUS_ADAPTER_RESET 0x85
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#define I2O_CMD_BUS_RESET 0x87
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#define I2O_CMD_BUS_SCAN 0x89
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#define I2O_CMD_BUS_QUIESCE 0x8b
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/*
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* Random Block Storage Class
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*/
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@@ -948,7 +1157,7 @@ extern void i2o_debug_state(struct i2o_controller *c);
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/* request queue sizes */
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#define I2O_MAX_SECTORS 1024
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#define I2O_MAX_SEGMENTS 128
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#define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
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#define I2O_REQ_MEMPOOL_SIZE 32
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